Datasheet

Rev. 3.00 Sep. 14, 2006 Page 403 of 408
REJ09B0105-0300
Item Page Revision (See Manual for Details)
Bit Bit Name Description
4 TCSRWE Timer Control/Status Register WD Write Enable
The WDON and WRST bits can be written when
the TCSRWE bit is set to 1.
When writing data to this bit, the value for bit 5
must be 0.
13.2.1 Timer Control/Status
Register WD (TCSRWD)
192
14.8.2 Mark State and Break
Sending
236 Replaced
Bit Bit Name Description
3 STOP Stop Condition Detection Flag
[Setting conditions]
• In master mode, when a stop condition is
detected after frame transfer
• In slave mode, when a stop condition is
detected after the general call address or
the first byte slave address, next to
detection of start condition, accords with the
address set in SAR
……
15.3.5 I
2
C Bus Status
Register (ICSR)
251
Figure 15.15 Receive Mode
Operation Timing
265
Bit 7 Bit 0 Bit 1
SDA
(Input)
7812
Bit 6
SCL
MST
15.7 Usage Notes 272 Added
16.3.1 A/D Data Registers A
to D (ADDRA to ADDRD)
276
There are four 16-bit read-only ADDR registers; ……
Therefore, byte access to ADDR should be done by reading the
upper byte first then the lower one. ADDR is initialized to H'0000.
Figure 17.2 Block Diagram
of Power-On Reset Circuit
and Low-Voltage Detection
Circuit
287
RES
C
RES
20.3 Electrical
Characteristics (Masked
ROM Version)
331
20.3 Electrical Characteristics (Masked ROM Version) [Preliminary]
The guarantee value for the electrical characteristics of masked ROM
version is preliminary.
20.3.1 Power Supply Voltage and Operating Ranges