Datasheet

Section 2 CPU
Rev. 3.00 Sep. 14, 2006 Page 37 of 408
REJ09B0105-0300
2.6 Basic Bus Cycle
CPU operation is synchronized by a system clock (φ). The period from a rising edge of φ to the
next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
T
1
state
Bus cycle
T
2
state
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Read data
Address
Write data
Internal data bus
(write access)
φ
Figure 2.9 On-Chip Memory Access Cycle