Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 47 of 408
REJ09B0105-0300
Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is
cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and
exception handling starts. Exception handling is the same as exception handling by the RES
pin.
• Trap Instruction
Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA
instruction generates a vector address corresponding to a vector number from 0 to 3, as
specified in the instruction code. Exception handling can be executed at all times in the
program execution state.
• Interrupts
External interrupts other than NMI and internal interrupts other than address break are masked
by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when
the current instruction or exception handling ends, if an interrupt request has been issued.
3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Relative Module Exception Sources
Vector
Number Vector Address Priority
RES pin
Watchdog timer
Reset 0 H'0000 to H'0001 High
 Reserved for system use 1 to 6 H'0002 to H'000D
External interrupt
pin
NMI 7 H'000E to H'000F
Trap instruction #0 8 H'0010 to H'0011
Trap instruction #1 9 H'0012 to H'0013
Trap instruction #2 10 H'0014 to H'0015
CPU
Trap instruction #3 11 H'0016 to H'0017 Low