Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 48 of 408
REJ09B0105-0300
Relative Module Exception Sources
Vector
Number Vector Address Priority
Address break Break conditions satisfied 12 H'0018 to H'0019 High
CPU Direct transition by executing
the SLEEP instruction
13 H'001A to H'001B
External interrupt
pin
IRQ0, low-voltage detection
interrupt
14 H'001C to H'001D
 Reserved for system use 15, 16 H'001E to H'0021
IRQ3 17 H'0022 to H'0023 External interrupt
pin
WKP 18 H'0024 to H'0025
 Reserved for system use 19, 20 H'0026 to H'0029
Timer W Timer W input capture A/
compare match A
Timer W input capture B/
compare match B
Timer W input capture C/
compare match C
Timer W input capture D/
compare match D
Timer W overflow
21 H'002A to H'002B
Timer V Timer V compare match A
Timer V compare match B
Timer V overflow
22 H'002C to H'002D
SCI3 SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
23 H'002E to H'002F
IIC2* IIC_2 transmit data empty
IIC_2 transmit end
IIC_2 receive error
24 H'0030 to H'0031
A/D converter A/D conversion end 25 H'0032 to H'0033
 Reserved for system use 26 to 28 H'0034 to H'0039
Timer B1* Timer B1 overflow 29 H'003A to H'003B
 Reserved for system use 30 to 33 H'003C to H'0043
Clock switch Clock switch (external clock to
on-chip oscillator clock)
34 H'0044 to H'0045 Low
Note: * Available for the H8/36912 Group only.