Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 49 of 408
REJ09B0105-0300
3.2 Register Descriptions
Interrupts are controlled by the following registers.
• Interrupt edge select register 1 (IEGR1)
• Interrupt edge select register 2 (IEGR2)
• Interrupt enable register 1 (IENR1)
• Interrupt enable register 2 (IENR2)
• Interrupt flag register 1 (IRR1)
• Interrupt flag register 2 (IRR2)
• Wakeup interrupt flag register (IWPR)
3.2.1 Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of the IRQ3 and IRQ0
pins.
Bit Bit Name
Initial
Value R/W Description
7  0 − Reserved
This bit is always read as 0.
6 to 4  All 1  Reserved
These bits are always read as 1.
3 IEG3 0 R/W IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
2, 1  All 0  Reserved
These bits are always read as 0.
0 IEG0 0 R/W IRQ0 Edge Select
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected