Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 51 of 408
REJ09B0105-0300
Bit Bit Name
Initial
Value R/W Description
0 IEN0 0 R/W IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0
pin are enabled.
3.2.4 Interrupt Enable Register 2 (IENR2)
IENR2 enables timer B1 interrupts.
Bit Bit Name
Initial
Value R/W Description
7  0  Reserved
This bit is always read as 0.
6  0 R/W Reserved
Although this bit is readable/writable, it should not be set
to 1.
5 IENTB1 0 R/W Timer B1 Interrupt Enable
When this bit is set to 1, overflow interrupt requests of
timer B1 are enabled.
4 to 0  All 1  Reserved
These bits are always read as 1.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.