Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 52 of 408
REJ09B0105-0300
3.2.5 Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag
[Setting condition]
• When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
• When IRRDT is cleared by writing 0
6  0  Reserved
This bit is always read as 0.
5, 4  All 1  Reserved
These bits are always read as 1.
3 IRRI3 0 R/W IRQ3 Interrupt Request Flag
[Setting condition]
• When IRQ3 pin is designated for interrupt input and
the designated signal edge is detected
[Clearing condition]
• When IRRI3 is cleared by writing 0
2, 1  All 0  Reserved
These bits are always read as 0.
0 IRRl0 0 R/W IRQ0 Interrupt Request Flag
[Setting condition]
• When IRQ0 pin is designated for interrupt input and
the designated signal edge is detected
[Clearing condition]
• When IRRI0 is cleared by writing 0