Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 54 of 408
REJ09B0105-0300
3.3 Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low for the specified period. To reset the chip
during operation, hold the RES pin low for the specified period. For details, refer to section 17,
Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits. When the RES pin goes
high after being held low for a certain period, this LSI starts reset exception handling. The reset
exception handling sequence is shown in figure 3.1.
The reset exception handling sequence is as follows.
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.