Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 55 of 408
REJ09B0105-0300
3.4 Interrupt Exception Handling
3.4.1 External Interrupts
As external interrupts, there are NMI, IRQ3, IRQ0, and WKP5 interrupts.
(1) NMI Interrupt
NMI interrupt is requested by input falling edge to the NMI pin. NMI is the highest interrupt, and
can always be accepted without depending on the I bit value in CCR.
(2) IRQ3 and IRQ0 Interrupts
IRQ3 and IRQ0 interrupts are requested by input signals to the IRQ3 and IRQ0 pins. These
interrupts are given different vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of the IEG3 and IEG0 bits in IEGR1.
When the IRQ3 and IRQ0 pins are designated for interrupt input in PMR1 and the designated
signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
These interrupts can be masked by setting the IEN3 and IEN0 bits in IENR1.
(3) WKP Interrupt
WKP interrupt is requested by an input signal to the WKP5 pin. This interrupt is detected by either
rising edge sensing or falling edge sensing, depending on the setting of the WPEG5 bit in IEGR2.
When the WKP5 pin is designated for interrupt input in PMR5 and the designated signal edge is
input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. This interrupt
can be masked by setting the IENWP bit in IENR1.