Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 56 of 408
REJ09B0105-0300
Vector fetch
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
RES
Internal
processing
Initial program
instruction prefetch
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
(2) (3)
(2)(1)
Reset cleared
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
Figure 3.1 Reset Sequence
3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For direct transfer interrupt requests generated by execution of a
SLEEP instruction, this function is included in IRR1 and IENR1.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable
bit.