Datasheet

Section 3 Exception Handling
Rev. 3.00 Sep. 14, 2006 Page 58 of 408
REJ09B0105-0300
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Vector fetch
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
RES
Internal
processing
Initial program
instruction prefetch
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
(2) (3)
(2)(1)
Reset cleared
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
Figure 3.2 Stack Status after Exception Handling