To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/38099 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series H8/38099F H8/38099 H8/38098 Rev.2.00 2007.
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Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface H8/38099 Group is single-chip microcontrollers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/38099 Group in the design of application systems.
Notes: When using an on-chip emulator (E8) for H8/38099 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E8, and cannot be used. 2. Pins P16, P36, and P37 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. Area H'020000 to H'020FFF must on no account be accessed. 4. Area H′FFA000 to H′FFA7FF must on no account be accessed. 5.
Application notes: Document Title Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464 All trademarks and registered trademarks are the property of their respective owners. Rev. 2.00 Jul.
Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 3 Pin Assignment ...................................................................................
3.4 3.5 Stack Status after Exception Handling................................................................................. 52 Usage Notes ......................................................................................................................... 53 3.5.1 Notes on Stack Area Use ........................................................................................ 53 3.5.2 Notes on Rewriting Port Mode Registers ............................................................... 54 3.5.
5.3 5.4 5.5 5.2.4 Selecting On-Chip Oscillator for System Clock ..................................................... 90 Subclock Generator.............................................................................................................. 91 5.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator............................................. 91 5.3.2 Pin Connection when not Using Subclock.............................................................. 92 5.3.3 How to Input the External Clock .....
6.4 6.5 Module Standby Function.................................................................................................. 123 Usage Notes ....................................................................................................................... 124 6.5.1 Standby Mode Transition and Pin States .............................................................. 124 6.5.2 Notes on External Input Signal Changes before/after Standby Mode................... 125 Section 7 ROM ....................
9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Port 3.................................................................................................................................. 160 9.2.1 Port Data Register 3 (PDR3)................................................................................. 160 9.2.2 Port Control Register 3 (PCR3) ............................................................................ 161 9.2.3 Port Pull-Up Control Register 3 (PUCR3).................................................
9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.9.2 Port Control Register A (PCRA) .......................................................................... 187 9.9.3 Pin Functions ........................................................................................................ 188 Port B ................................................................................................................................. 190 9.10.1 Port Data Register B (PDRB) ...................................................
10.4 Operation ........................................................................................................................... 222 10.4.1 Initial Settings of Registers after Power-On ......................................................... 222 10.4.2 Initial Setting Procedure ....................................................................................... 222 10.4.3 Data Reading Procedure ....................................................................................... 223 10.
12.6 Usage Notes ....................................................................................................................... 248 12.6.1 16-Bit Timer Mode ............................................................................................... 248 12.6.2 8-Bit Timer Mode ................................................................................................. 248 12.6.3 Flag Clearing ...................................................................................................
14.4 14.5 14.6 14.7 14.8 14.3.9 Timer Synchro Register (TSYR) .......................................................................... 287 Interface to CPU ................................................................................................................ 288 14.4.1 16-Bit Registers .................................................................................................... 288 14.4.2 8-Bit Registers .................................................................................
15.4.1 16-Bit Counter Operation ..................................................................................... 328 15.4.2 8-Bit Counter Operation ....................................................................................... 329 15.4.3 IRQAEC Operation............................................................................................... 330 15.4.4 Event Counter PWM Operation............................................................................ 330 15.4.
17.4 17.5 17.6 17.7 17.8 17.9 17.3.11 IrDA Control Register (IrCR) ............................................................................... 376 17.3.12 Serial Extended Mode Register (SEMR) .............................................................. 377 Operation in Asynchronous Mode ..................................................................................... 378 17.4.1 Clock...............................................................................................................
18.3.2 Serial Control/Status Register 4 (SCSR4) ............................................................ 418 18.3.3 Transmit Data Register 4 (TDR4)......................................................................... 421 18.3.4 Receive Data Register 4 (RDR4) .......................................................................... 421 18.3.5 Shift Register 4 (SR4)........................................................................................... 421 18.4 Operation ..........................
20.4 Operation ........................................................................................................................... 446 20.4.1 A/D Conversion .................................................................................................... 446 20.4.2 External Trigger Input Timing.............................................................................. 447 20.4.3 Operating States of A/D Converter ....................................................................... 447 20.
2 22.4 22.5 22.6 22.7 22.3.7 I C Bus Transmit Data Register (ICDRT) ............................................................ 494 2 22.3.8 I C Bus Receive Data Register (ICDRR).............................................................. 494 2 22.3.9 I C Bus Shift Register (ICDRS)............................................................................ 494 Operation ........................................................................................................................... 495 2 22.
Section 26 Electrical Characteristics .................................................................547 26.1 Absolute Maximum Ratings for F-ZTAT Version............................................................. 547 26.2 Electrical Characteristics for F-ZTAT Version.................................................................. 548 26.2.1 Power Supply Voltage and Operating Range........................................................ 548 26.2.2 DC Characteristics ....................................
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Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8/38099 Group................................................................. 3 Figure 1.2 Pin Assignment of H8/38099 Group (PLQP0100KB-A) .............................................. 4 Section 2 CPU Figure 2.1 Memory Map............................................................................................................... 13 Figure 2.2 CPU Registers ...................................................................................
Figure 5.4 Example of External Clock Input ................................................................................ 89 Figure 5.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator................................ 91 Figure 5.6 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 92 Figure 5.7 Pin Connection when not Using Subclock .................................................................. 92 Figure 5.
Figure 10.2 Definition of Time Expression ................................................................................ 218 Figure 10.3 Initial Setting Procedure .......................................................................................... 222 Figure 10.4 Example: Reading of Inaccurate Time Data............................................................ 223 Section 11 Timer C Figure 11.1 Block Diagram of Timer C................................................................................
Figure 14.14 Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Figure 14.25 Figure 14.26 Figure 14.27 Figure 14.28 Figure 14.29 Figure 14.30 Figure 14.31 Figure 14.32 Figure 14.33 Figure 14.34 Figure 14.35 Figure 14.36 Figure 14.37 Example of Synchronous Operation...................................................................... 297 Setting Procedure for Operation with Cascaded Operation...................................
Figure 17.2 Data Format in Asynchronous Communication ...................................................... 378 Figure 17.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)............. 379 Figure 17.4 Sample SCI3 Initialization Flowchart...................................................................... 383 Figure 17.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) .............
Figure 18.9 Relationship between Reading RDR4 and RDRF ................................................... 431 Figure 18.10 Transfer Format when Internal Clock of φ/2 is Selected ....................................... 431 Section 19 14-Bit PWM Figure 19.1 Block Diagram of 14-Bit PWM .............................................................................. 433 Figure 19.2 Example of Waveform Produced by Pulse-Division Type PWM (Division by 4) ............................................................
Figure 22.10 Figure 22.11 Figure 22.12 Figure 22.13 Figure 22.14 Figure 22.15 Figure 22.16 Figure 22.17 Figure 22.18 Figure 22.19 Figure 22.20 Figure 22.21 Slave Transmit Mode Operation Timing (2) ......................................................... 502 Slave Receive Mode Operation Timing (1)........................................................... 503 Slave Receive Mode Operation Timing (2)........................................................... 504 Clock Synchronous Serial Transfer Format .....
Figure 26.16 Figure 26.17 Figure 26.18 Figure 26.19 Figure 26.20 Figure 26.21 Figure 26.22 Figure 26.23 Input Timing.......................................................................................................... 598 SCK3 Input Clock Timing .................................................................................... 599 SCI3 Input/Output Timing in Clock Synchronous Mode...................................... 599 Clock Input Timing for TCLKA to TCLKC Pins ...................................
Figure B.12 (g) Port E Block Diagram (PE1)............................................................................. 655 Figure B.12 (h) Port E Block Diagram (PE0)............................................................................. 656 Figure B.13 (a) Port F Block Diagram (PF3).............................................................................. 657 Figure B.13 (b) Port F Block Diagram (PF2) ............................................................................. 658 Figure B.
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Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 21 Table 2.2 Data Transfer Instructions....................................................................................... 22 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Section 7 ROM Table 7.1 Setting Programming Modes ................................................................................ 134 Table 7.2 Boot Mode Operation ........................................................................................... 136 Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ........................................................................................ 137 Table 7.4 Reprogram Data Computation Table .....................
Table 14.12 Table 14.13 PWM Output Registers and Output Pins .......................................................... 301 TPU Interrupts .................................................................................................. 305 Section 15 Asynchronous Event Counter (AEC) Table 15.1 Pin Configuration.................................................................................................. 320 Table 15.2 Examples of Event Counter PWM Operation...........................................
Section 18 Serial Communication Interface 4 (SCI4) Table 18.1 Pin Configuration.................................................................................................. 414 Table 18.2 Prescaler Division Ratio and Transfer Clock Cycle (Internal Clock) ................... 420 Table 18.3 SCI4 Interrupt Sources.......................................................................................... 429 Section 19 14-Bit PWM Table 19.1 Pin Configuration..................................................
Table 26.11 Table 26.12 Table 26.13 Table 26.14 Table 26.15 Table 26.16 Table 26.17 Table 26.18 Table 26.19 Appendix Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5 Absolute Maximum Ratings ............................................................................. 575 DC Characteristics ............................................................................................ 580 Control Signal Timing ...............................................................................
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Section 1 Overview Section 1 Overview 1.
Section 1 Overview • On-chip memory Product Classification Model ROM RAM Flash memory version (F-ZTATTM version) H8/38099F HD64F38099 128 Kbytes 4 Kbytes Masked ROM version H8/38099 HD64338099 128 Kbytes 4 Kbytes H8/38098 HD64338098 96 Kbytes 2 Kbytes Note: F-ZTAT TM is a trademark of Renesas Technology Corp. • General I/O ports I/O pins: 75 I/O pins, including 4 large current ports (IOL = 15 mA, @VOL = 1.
Section 1 Overview Internal Block Diagram X1 X2 OSC1 OSC2 Vcc AVcc Vss Vss/AVss RES TEST/ADTRG NMI *2 Subclock pulse generator System clock pulse generator H8/300H CPU P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16 P70/SEG17 P71/SEG18 P72/SEG19 P73/SEG20 P74/SEG21 P75/SEG22 P76/SEG23 P77/SEG24 Timer pulse unit Asynchronous event counter Timer C Timer F Timer G Port 9 P90/PWM1 P91/PWM2 P92/IRQ4/PWM3 P93/PWM4 14-bit PWM1 14-bit PWM2 PA0/COM1 PA1/COM2 PA2/COM3 PA3
Section 1 Overview Pin Assignment 51 52 54 53 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 39 87 PLQP0100KB-A (Top view) 88 89 38 37 24 25 23 22 21 20 19 18 17 16 15 P40/SCK31/TMIF C2 C1 V3 V2 V1 (also used for 3V booster) PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 PC7/SEG40 PC6/SEG39 PC5/SEG38 PC4/SEG37 PC3/SEG36 PC2/SEG35 PC1/SEG34 PC0/SEG33 P87/SEG32 P86/SEG31 P85/SEG30 P
Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Type Symbol Pin No. I/O Functions Power supply pins Vcc 90 Input Power supply pin. Connect this pin to the system power supply. Vss 88, 66 (= AVss) Input Ground pins. Connect these pins to the system power supply (0 V). AVcc 75 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. AVss 66 (= Vss) Input Ground pin for the A/D converter.
Section 1 Overview Type Symbol Pin No. I/O Functions System control RES 86 Input Reset pin. The power-on reset circuit is incorporated. When externally driven low, the chip is reset. TEST 65 Input Test pin. Also used as the ADTRG pin. When this pin is not used as the ADTRG pin, users cannot use this pin. Connect this pin to Vss. When this pin is used as the ADTRG pin, see section 20.4.2, External Trigger Input Timing. NMI 83 Input NMI interrupt request pin.
Section 1 Overview Type Symbol Pin No. I/O Functions 16-bit timer pulse unit (TPU) TIOCA1 79 I/O Pin for the TGR1A input capture input or output compare output, or PWM output. TIOCB1 80 I/O Pin for the TGR1B input capture input or output compare output, or PWM output. TIOCA2 81 I/O Pin for the TGR2A input capture input or output compare output, or PWM output. TIOCB2 82 I/O Pin for the TGR2B input capture input or output compare output, or PWM output.
Section 1 Overview Type Symbol Pin No. I/O 14-bit PWM PWM1 97 PWM2 98 Output Output pins for waveforms generated by the 14-bit PWM in PWM channels 1, 2, 3, and 4. Output PWM3 99 Output PWM4 100 Output Serial SCK4 communications interface 4 SI4 (SCI4) (F-ZTAT version only) SO4 91 I/O Transfer clock pin for SCI4 data transmission/reception. When the E8 or on-chip emulator debugger is used, this pin is not available. 93 Input SCI4 data input pin.
Section 1 Overview Type Symbol Pin No. I/O Functions A/D converter AN0 to AN7 74 to 67 Input Analog data input pins for the A/D converter. ADTRG 65 Input External trigger input pin for the A/D converter. SDA 95 I/O IIC data I/O pin. SCL 94 I/O IIC clock I/O pin. COM1 to COM4 41 to 44 Output LCD common output pins. SEG1 to SEG8 1 to 8 Output LCD segment output pins.
Section 1 Overview Type Symbol Pin No. I/O Functions I/O ports P70 to P77 17 to 24 I/O 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 7 (PCR7). P80 to P87 25 to 32 I/O 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 8 (PCR8). P90 to P93 97 to 100 I/O 4-bit I/O pins. Input or output can be designated for each bit by means of the port control register 9 (PCR9).
Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H can handle a 16-Mbyte linear address space and is ideal for realtime control. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added.
Section 2 CPU • Two types of CPU operating modes Normal mode Advanced mode Note: Normal mode cannot be used in this LSI. • Power-down state Transition to power-down state by SLEEP instruction Rev. 2.00 Jul.
Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 16 Mbytes, which includes the program area and the data area. Figure 2.1 shows the memory map.
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between the stack pointer and the stack area. Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute.
Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 0 MSB LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 2.00 Jul.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined in table 2.1. Table 2.
Section 2 CPU Symbol Description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (
Section 2 CPU Instruction Size* Function BLD B ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B ¬ C → (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev. 2.00 Jul.
Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction.
Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes.
Section 2 CPU (1) Register DirectRn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory.
Section 2 CPU Table 2.11 shows the access ranges of absolute addresses. Table 2.11 Absolute Address Access Ranges Absolute Address Access Range 8 bits (@aa:8) H'FFFF00 to H'FFFFFF (16776960 to 16777215) 16 bits (@aa:16) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32767, 16744448 to 16777215) 24 bits (@aa:24) H'000000 to H'FFFFFF (0 to 16777215) (6) Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand.
Section 2 CPU (8) Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed in words, generating a 16-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF).
Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 25.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. For the program halt state, there are sleep (high-speed or medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions.
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Section 2 CPU 2.8.3 Bit-Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units.
Section 2 CPU Example 2: When the BSET instruction is executed for port 5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
Section 2 CPU 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction. As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. • Prior to executing BSET instruction MOV.B MOV.B MOV.
Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.
Section 2 CPU • Prior to executing BCLR instruction MOV.B MOV.B MOV.B H'3F, R0L R0L, @RAM0 R0L, @PCR5 The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.
Section 3 Exception Handling 3.2 Reset A reset has the highest exception priority. Table 3.2 shows the three sources that cause a reset. Table 3.2 Interrupt Sources that Cause a Reset Origin of Interrupt Source Description RES pin Low-level input Power-on reset circuit Rising of the power-supply voltage (Vcc) For details, see section 23, Power-On Reset Circuit. Watchdog timer Counter overflow For details, see section 16, Watchdog Timer. 3.2.
Section 3 Exception Handling Internal processing Vector fetch Prefetch of first program instruction φ RES Internal address bus (1) (3) (5) Internal read signal Internal write signal Internal data bus (16 bits) (1), (3) (2), (4) (5) (6) (2) (4) (6) Reset exception handling vector address (1) = H'000000, (3) = H'000002 Start address (contents of reset exception handling vector address) Start address Initial program instruction Figure 3.1 Reset Exception Handling Sequence 3.2.
Section 3 Exception Handling 3.3 Interrupts The interrupt sources include 14 external interrupts (NMI, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, and WKP7 to WKP0) and 28 internal interrupts (for the flash memory version) or 27 internal interrupts (for the masked ROM version) from on-chip peripheral modules. Figure 3.2 shows the interrupt sources and their numbers.
Section 3 Exception Handling 3.4 Stack Status after Exception Handling Figures 3.3 shows the stack after completion of interrupt exception handling.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Notes on Stack Area Use When word data or longword data is accessed in this LSI, the least significant bit of the address is regarded as 0. The stack must always be accessed in word units or longword units, and the stack pointer (SP: ER7) should never indicate an odd address. Use PUSH.W Rn (MOV.W Rn, @–SP) or PUSH.L ERn (MOV.L ERn, @–SP) to save register values. To restore register values, use POP.W Rn (MOV.W @SP+, Rn) or POP.L ERn (MOV.L @SP+, ERn).
Section 3 Exception Handling 3.5.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins and when the value of the ECPWME bit in AEGSR is rewritten to switch between selection and nonselection of IRQAEC, the following points should be observed.
Section 3 Exception Handling Table 3.3 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 IRR1 IRRI4 Conditions When the IRQ4 bit in PMR9 or PMRF is changed from 0 to 1 while the IRQ4 pin is low and the IEG4 bit in IEGR is 0. When the IRQ4 bit in PMR9 or PMRF is changed from 1 to 0 while the IRQ4 pin is low and the IEG4 bit in IEGR is 1. IRRI3 When the IRQ3 bit in PMRB or PMRE is changed from 0 to 1 while the IRQ3 pin is low and the IEG3 bit in IEGR is 0.
Section 3 Exception Handling Figure 3.5 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. This procedure also applies to AEGSR setting. When switching a pin function, mask the interrupt before setting the bit in the port mode register (or AEGSR). After accessing the port mode register (or AEGSR), execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0.
Section 3 Exception Handling 3.5.3 Method for Clearing Interrupt Request Flags Use the recommended method given below when clearing the flags in interrupt request registers (IRR1, IRR2, and IWPR). (1) Recommended method Use a single instruction to clear flags. The bit manipulation instruction and byte-size data transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 in IRR1) are given below. BCLR #1, @IRR1:8 MOV.
Section 3 Exception Handling Rev. 2.00 Jul.
Section 4 Interrupt Controller Section 4 Interrupt Controller 4.1 Features This LSI includes an interrupt controller, which has the following features. • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Three mask levels can be set for each module for all interrupts except an NMI and address break. • Interrupts can be enabled or disabled in three levels by the INTM1 and INTM0 bits in the interrupt mask register (INTM).
Section 4 Interrupt Controller 4.2 Input/Output Pins Table 4.1 shows the pin configuration of the interrupt controller. Table 4.1 Pin Configuration Pin Name I/O Function NMI Input Nonmaskable external interrupt pin Rising or falling edge can be selected IRQAEC Input Maskable external interrupt pin Rising, falling, or both edges can be selected IRQ4 Input IRQ3 Input Maskable external interrupt pins Rising or falling edge can be selected IRQ1 Input IRQ0 Input WKP7 to WKP0 Input 4.
Section 4 Interrupt Controller 4.3.1 Interrupt Edge Select Register (IEGR) IEGR selects the sense of an edge that generates interrupt requests of the NMI, TMIF, ADTRG, IRQ4, IRQ3, IRQ1, and IRQ0 pins.
Section 4 Interrupt Controller 4.3.2 Wakeup Edge Select Register (WEGR) WEGR selects the sense of an edge that generates interrupt requests of the WKP7 to WKP0 pins.
Section 4 Interrupt Controller 4.3.3 Interrupt Enable Register 1 (IENR1) IENR1 enables the RTC, WKP7 to WKP0, IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC interrupts. Bit Bit Name Initial Value R/W 7 IENRTC 0 R/W Description RTC Interrupt Request Enable The RTC interrupt request is enabled when this bit is set to 1. 6 1 Reserved This bit is always read as 1 and cannot be modified.
Section 4 Interrupt Controller 4.3.4 Interrupt Enable Register 2 (IENR2) IENR2 enables the direct transition, A/D converter, timer G, timer F, timer C, and asynchronous event counter interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transition Interrupt Request Enable The direct transition interrupt request is enabled when this bit is set to 1.
Section 4 Interrupt Controller 4.3.5 Interrupt Request Register 1 (IRR1) IRR1 indicates the IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC interrupt request status. Bit Initial Bit Name Value R/W Description 7 to 5 Reserved All 1 These bits are always read as 1 and cannot be modified.
Section 4 Interrupt Controller Bit Initial Bit Name Value R/W Description 0 IRRI0 R/W IRQ0 Interrupt Request Flag 0 [Setting condition] The IRQ0 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 4.3.6 Interrupt Request Register 2 (IRR2) IRR2 indicates the state of the direct transition, A/D converter, timer G, timer F, timer C, and asynchronous event counter interrupt requests.
Section 4 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 IRRTFH 0 R/W Timer FH Interrupt Request Flag [Setting condition] The timer FH compare match or overflow occurs [Clearing condition] Writing of 0 to this bit 2 IRRTFL 0 R/W Timer FL Interrupt Request Flag [Setting condition] The timer FL compare match or overflow occurs [Clearing condition] Writing of 0 to this bit 1 IRRTC 0 R/W Timer C Interrupt Request Flag [Setting condition] The timer C overflow or underflow o
Section 4 Interrupt Controller 4.3.7 Wakeup Interrupt Request Register (IWPR) IWPR has the WKP7 to WKP0 interrupt request status flags.
Section 4 Interrupt Controller Bit Bit Name Initial Value R/W Description 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] The WKP2 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 1 IWPF1 0 R/W WKP1 Interrupt Request Flag [Setting condition] The WKP1 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 0 IWPF0 0 R/W WKP0 Interrupt Request F
Section 4 Interrupt Controller 4.3.8 Interrupt Priority Registers A to F (IPRA to IPRF) IPR sets mask levels (levels 2 to 0) for interrupts other than the NMI and address break. The correspondence between interrupt sources and IPR settings is shown in table 4.2. Setting a value in the range from H'0 to H'3 in the 2-bit groups of bits 7 and 6, 5 and 4, 3 and 2, and 1 and 0 sets the mask level of the corresponding interrupt. Bits 3 to 0 in IPRE and bits 1 and 0 in IPRF are reserved.
Section 4 Interrupt Controller 4.3.9 Interrupt Mask Register (INTM) INTM is an 8-bit readable/writable register that controls 3-level interrupt masking depending on the combination of the INTM0 and INTM1 bits. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved These bits are always read as 1 and cannot be modified. 1 INTM1 0 R/W Set the interrupt mask level.
Section 4 Interrupt Controller When exception handling for the WKP7 to WKP0 interrupts is accepted, the I bit in CCR is set to 1. The interrupt mask level can be set by IPR. (3) IRQ4, IRQ3, IRQ1, and IRQ0 Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 interrupts are requested by input signals at IRQ4, IRQ3, IRQ1, and IRQ0 pins. Using the IEG4, IEG3, IEG1, and IEG0 bits in IEGR, it is possible to select whether an interrupt is generated by a rising or falling edge at IRQ4, IRQ3, IRQ1, and IRQ0 pins.
Section 4 Interrupt Controller 4.4.2 Internal Interrupts Internal interrupts generated from the on-chip peripheral modules have the following features: • For each on-chip peripheral module, there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. Internal interrupts can be controlled independently. If an enable bit is set to 1, an interrupt request is sent to the interrupt controller. • The interrupt mask level can be set by IPR.
Section 4 Interrupt Controller Table 4.
Section 4 Interrupt Controller Origin of Interrupt Source Name Vector Number Vector Address IPR Mask Level High WDT WDT overflow (interval timer) 27 H'00006C IPRB3, IPRB2 AEC AEC overflow 28 H'000070 IPRB1, IPRB0 TPU_1 TG1A (TG1A input capture/compare match) 29 H'000074 IPRC7, IPRC6 TG1B (TG1B input capture/compare match) 30 H'000078 TCI1V (overflow 1) 31 H'00007C TG2A (TG2A input capture/compare match) 32 H'000080 TG2B (TG2B input capture/compare match) 33 H'000084 TCI2V (o
Section 4 Interrupt Controller Origin of Interrupt Source Name Vector Number Vector Address IPR Mask Level High Timer C Timer C overflow/underflow 53 H'0000D4 IPRF7, IPRF6 Timer G Timer G input capture Timer G overflow 54 H'0000D8 IPRF5, IPRF4 SCI3_3 Transmit completion/transmit data empty Receive data full/overrun error Framing error/parity error 55 H'0000DC IPRF3, IPRF2 Note: * Supported only by the flash version. Rev. 2.00 Jul.
Section 4 Interrupt Controller 4.6 Operation NMI and address break interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts, WKP interrupts, and on-chip peripheral module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 4.3 shows the interrupt control states. Figure 4.
Section 4 Interrupt Controller 3. If a conflict occurs between interrupt requests that are not held pending due to the settings of the IMTM1, IMTN0 bits in INTM or the I bit in CCR, the interrupt request with the highest mask level according to table 4.2 is selected regardless of the IPR setting. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5.
Section 4 Interrupt Controller Program execution state Interrupt generated? No Yes NMI or address break? No Yes No INTM1 = 0? INTM0 = 0? INTM1 = 0? INTM0 = 1? Yes Yes No I = 0? Mask level 1 or 2 interrupt? Yes No No Mask level 2 interrupt? No Yes No Yes No I = 0? I = 0? Yes Yes Save PC and CCR Held pending I←1 Set vector address Branch to interrupt handling routine Figure 4.2 Flowchart of Procedure Up to Interrupt Acceptance 4.6.1 Interrupt Exception Handling Sequence Figure 4.
REJ09B0309-0200 Rev. 2.00 Jul. 04, 2007 Page 80 of 692 Internal data bus (4) High (3) Internal processing (6) (5) Stack (8) (7) (10) (9) Vector fetch Figure 4.
Section 4 Interrupt Controller 4.6.2 Interrupt Response Times Table 4.4 shows interrupt response times − the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 4.4 Interrupt Response Times (States) No.
Section 4 Interrupt Controller 4.7 Usage Notes 4.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction.
Section 4 Interrupt Controller 4.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. When an interrupt request is generated, an interrupt is requested to the CPU after the interrupt controller has determined the mask level. At that time, if the CPU is executing an instruction that disables interrupts, the CPU always executes the next instruction after the instruction execution is completed. 4.7.
Section 4 Interrupt Controller Rev. 2.00 Jul.
Section 5 Clock Pulse Generator Section 5 Clock Pulse Generator The clock pulse generator incorporated into this LSI consists of a system clock pulse generator circuit that consists of a system clock oscillator, system clock divider, and an on-chip oscillator for the system clock, and a subclock pulse generator circuit that consists of a subclock oscillator and subclock divider. Figure 5.1 is a block diagram of the clock pulse generator.
Section 5 Clock Pulse Generator 5.1 Register Description • SUB32k control register (SUB32CR) • Oscillator Control Register (OSCCR) 5.1.1 SUB32k Control Register (SUB32CR) SUB32CR controls whether the subclock oscillator is operating or stopped. Bit Bit Name Initial Value R/W 7 32KSTOP 0 R/W Description Subclock Oscillator Operation Control Controls whether the subclock oscillator is operating or stopped. When the subclock oscillator is not used, set this bit to 1.
Section 5 Clock Pulse Generator 5.1.2 Oscillator Control Register (OSCCR) OSCCR is used to control the built-in feedback resistor and includes the IRQAEC and OSC flags. Bit Bit Name Initial Value R/W 7 — 0 R/W Description Reserved This bit can be read from or written to.
Section 5 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 1 OSCF —* R OSC Flag This bit indicates which oscillator is acting as the system clock pulse generator. 0: The system clock oscillator is the generator (operation of the on-chip oscillator for system clock stopped) 1: The on-chip oscillator for the system clock is the generator (system clock oscillator stopped) 0 — 0 R/W Reserved The write value should always be 0. Note: 5.
Section 5 Clock Pulse Generator 5.2.2 Connecting Ceramic Resonator Figure 5.3 shows a typical method of connecting a ceramic resonator. C1 OSC1 C2 OSC2 Frequency Manufacturer Product Type C 1 , C2 Recommended Value 4.194 MHz Murata Manufacturing CSTLS4M19G53-B0 15 pF (on-chip) CSTLS4M19G56-B0 47 pF (on-chip) Co., Ltd. Figure 5.3 Typical Connection to Ceramic Resonator 5.2.3 External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.
Section 5 Clock Pulse Generator 5.2.4 Selecting On-Chip Oscillator for System Clock The on-chip oscillator is selected by the input level on the IRQAEC pin during a reset*. The selection of the system clock oscillator or on-chip oscillator for the system clock is as listed in table 5.1. The level being input on the IRQAEC pin during a reset should be fixed to either Vcc or GND, depending on the oscillator type to be selected.
Section 5 Clock Pulse Generator 5.3 Subclock Generator Subclocks can be supplied either by connecting a crystal resonator, or by providing external clock input. 5.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator Figure 5.5 shows an example of connection to a 32.768-kHz or 38.4-kHz crystal resonator. Notes in section 5.5.2, Notes on Board Design, also apply to this connection. C1 X1 X2 Note: Consult with the crystal resonator manufacturer to determine the circuit constants.
Section 5 Clock Pulse Generator Figure 5.6 shows the equivalent circuit of the crystal resonator. CS LS RS X1 X2 CO C O = 0.9 pF (typ.) R S = 50 kΩ (typ.) φW = 32.768 kHz/38.4kHz Figure 5.6 Equivalent Circuit of 32.768-kHz Crystal Resonator 5.3.2 Pin Connection when not Using Subclock When the subclock is not used, connect the X1 pin to GND and leave the X2 pin open, as shown in figure 5.7. X1 GND X2 Open Figure 5.7 Pin Connection when not Using Subclock Rev. 2.00 Jul.
Section 5 Clock Pulse Generator 5.3.3 How to Input the External Clock Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 5.8. X1 X2 External clock input Open Figure 5.8 Pin Connection when Inputting External Clock Frequency Subclock (φw) Duty 45% to 55% Rev. 2.00 Jul.
Section 5 Clock Pulse Generator 5.4 Prescalers This LSI has two prescalers (prescaler S and prescaler W), and each has its own input clock signal. Prescaler S is a 17-bit counter that has the system clock (φ) as its input clock. Its prescaled outputs provide the internal clock signals that drive the on-chip peripheral modules. Prescaler W is an 8-bit counter that has a frequency-divided signal (φW/4) derived from the watch clock (φW) as its input clock.
Section 5 Clock Pulse Generator 5.5 Usage Notes 5.5.1 Note on Resonators and Resonator Circuits Resonator characteristics are closely related to board design. Therefore, resonators should be assigned after being carefully evaluated by the user in the masked ROM version and flash memory version, with referring to the examples shown in this section. Resonator circuit constants will differ depending on a resonator, stray capacitance in its mounting circuit, and other factors.
Section 5 Clock Pulse Generator Figure 5.10 (1) shows an example measuring circuit with the negative resistance recommended by the resonator manufacturer. Note that if the negative resistance of the circuit is less than that recommended by the resonator manufacturer, it may be difficult to start the main oscillator.
Section 5 Clock Pulse Generator 5.5.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.11). Avoid Signal A Signal B C1 OSC1 C2 OSC2 Figure 5.
Section 5 Clock Pulse Generator (2) Wait Time After the system clock is generated, the time required for the amplitude of the oscillation waveform to increase, the oscillation frequency to stabilize, and the CPU and peripheral functions to begin operating.
Section 5 Clock Pulse Generator 5.5.5 Note on the Oscillation Stabilization of Resonators When a microcontroller operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. Depending on the individual resonator characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential.
Section 5 Clock Pulse Generator Rev. 2.00 Jul.
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has eight modes of operation after a reset. These include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by selectively halting on-chip module functions. • Active (medium-speed) mode The CPU and all on-chip peripheral modules are operable on the system clock.
Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are as follows. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • System control register 3 (SYSCR3) • Clock halt registers 1 to 3 (CKSTPR1 to CKSTPR3) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes with SYSCR2 and SYSCR3.
Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 LSON 0 R/W Selects the system clock (φ) or subclock (φSUB) as the CPU operating clock when watch mode is cleared. 0: The CPU operates on the system clock (φ) 1: The CPU operates on the subclock (φSUB) 2 TMA3 0 R/W Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY and LSON in SYSCR1 and bits DTON and MSON in SYSCR2. For details, see table 6.2.
Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes with SYSCR1 and SYSCR3. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1 and cannot be modified. 4 NESEL 1 R/W Noise Elimination Sampling Frequency Select This bit selects the sampling frequency of φOSC when φW is sampled. When a system clock is used, clear this bit to 0.When the on-chip oscillator is selected, set this bit to 1.
Section 6 Power-Down Modes 6.1.3 System Control Register 3 (SYSCR3) SYSCR3 controls the power-down modes with SYSCR1 and SYSCR2. Bit Bit Name Initial Value R/W Description 7 to 1 All 1 Reserved These bits are always read as 1 and cannot be modified. 0 STS3 0 R/W Standby Timer Select 3 Specifies the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or watch mode to active mode or sleep mode.
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Wait Time Bit Operating Frequency and Wait Time Number of STS3 STS2 STS1 STS0 Wait States 10 MHz 8 MHz 6 MHz 5 MHz 4.194 MHz 3 MHz 2 MHz 0 0 0 0 8,192 states 819.2 1,024.0 1,365.3 1,638.4 1,953.3 2,730.7 4,096.0 0 0 0 1 16,384 states 1,638.4 2,048.0 2,730.7 3,276.8 3,906.5 5,461.3 8,192.0 0 0 1 0 1,024 states 102.4 128.0 170.7 204.8 244.2 341.3 512.0 0 0 1 1 2,048 states 204.8 256.0 341.
Section 6 Power-Down Modes 6.1.4 Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3) CKSTPR1, CKSTPR2, and CKSTPR3 allow the on-chip peripheral modules to enter the standby state in module units. • CKSTPR1 Bit 7 Initial Value R/W Bit Name 1 3 S4CKSTP* * 1 R/W Description SCI4 Module Standby The SCI4 enters standby mode when this bit is cleared to 0. 6 S31CKSTP 1 R/W SCI3_1 Module Standby* 2 The SCI3_1 enters standby mode when this bit is cleared to 0.
Section 6 Power-Down Modes • CKSTPR2 Bit Bit Name Initial Value R/W Description 7 ADBCKSTP 1 R/W Address Break Module Standby The address break enters standby mode when this bit is cleared to 0. 6 TPUCKSTP 1 R/W TPU Module Standby The TPU enters standby mode when this bit is cleared to 0. 5 IICCKSTP 1 R/W IIC2 Module Standby The IIC2 enters standby mode when this bit is cleared to 0. 4 PW2CKSTP 1 R/W PWM2 Module Standby The PWM2 enters standby mode when this bit is cleared to 0.
Section 6 Power-Down Modes • CKSTPR3 Bit Bit Name Initial Value R/W Description 7 S33CKSTP 1 R/W SCI3_3 Module Standby* 2 The SCI3_3 enters standby mode when this bit is cleared to 0. 6 TCCKSTP 1 R/W Timer C Module Standby The timer C enters standby mode when this bit is cleared to 0. 5 TGCKSTP 1 R/W Timer G Module Standby The timer G enters standby mode when this bit is cleared to 0. 4 PW4CKSTP 1 R/W PWM4 Module Standby The PWM4 enters standby mode when this bit is cleared to 0.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. The program execution state is recovered from the program halt state by an interrupt. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program.
Section 6 Power-Down Modes Program execution state Reset state Program SLEEP d instruction halt state Standby Active (high-speed mode) a P n E E tio SL truc s in g d SLEEP instruction f SLEEP instruction P n EE tio SL truc s in SLEEP instruction Sleep (high-speed) mode 3 4 mode Program halt state SLEEP instruction a 4 b SLEEP b instruction Active (medium-speed) mode e SLEEP instruction 1 j SLEEP instruction S ins LE tru EP cti on e i 1 SLEEP instruction SLEEP instruction c Sub
Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling Transition Mode after SLEEP State Transition Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Active (highspeed) mode Symbol in Figure 6.
Section 6 Power-Down Modes Transition Mode after SLEEP State Transition Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Active (mediumspeed) mode Symbol in Figure 6.
Section 6 Power-Down Modes Transition Mode after SLEEP State Transition Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Subactive mode Symbol in Figure 6.
Section 6 Power-Down Modes Table 6.
Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the system clock oscillator, on-chip oscillator for the system clock, subclock oscillator, and on-chip peripheral modules continues operating. In sleep (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. Sleep mode is cleared by an interrupt.
Section 6 Power-Down Modes 6.2.3 Watch Mode In watch mode, the system clock oscillator, on-chip oscillator for the system clock, and CPU operation stop and on-chip peripheral modules stop functioning except for the WDT, RTC, timer C, timer F, timer G, asynchronous event counter, and LCD controller/driver. However, as long as the rated voltage is supplied, the contents of CPU registers, some on-chip peripheral module registers, and on-chip RAM are retained.
Section 6 Power-Down Modes 6.2.5 Subactive Mode In subactive mode, the system clock oscillator and the on-chip oscillator for the system clock stop functioning but on-chip peripheral modules other than the A/D converter, PWM, TPU, and IIC2 continue to operate. As long as a required voltage is applied, the contents of some registers of the on-chip peripheral modules are retained. Subactive mode is cleared by the SLEEP instruction.
Section 6 Power-Down Modes 6.3 Direct Transition The CPU can execute programs in two modes: active and subactive modes. A direct transition is made between these two modes without stopping program execution. A direct transition can also be made when the operating clock is changed in active and subactive modes. The transition is made via the sleep or watch mode, by setting the DTON bit in SYSCR2 to 1 to execute a SLEEP instruction.
Section 6 Power-Down Modes 6.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY, TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2).
Section 6 Power-Down Modes 6.3.4 Direct Transition from Active (Medium-Speed) Mode to Subactive Mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY, LSON, and TMA3 bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4).
Section 6 Power-Down Modes 6.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed.
Section 6 Power-Down Modes 6.3.7 (1) Notes on External Input Signal Changes before/after Direct Transition Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode. (2) Direct transition from active (medium-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 6.5.
Section 6 Power-Down Modes 6.5 Usage Notes 6.5.1 Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while the SSBY and TMA3 bits in SYSCR1 are set to 1 and the LSON bit in SYSCR1 is cleared to 0, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 6.2 shows the timing in this case.
Section 6 Power-Down Modes 6.5.2 (1) Notes on External Input Signal Changes before/after Standby Mode When External Input Signal Changes before/after Standby Mode or Watch Mode When an external input signal such as NMI, IRQ, WKP, or IRQAEC is input, both the high- and low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB (referred to together in this section as the internal clock).
Section 6 Power-Down Modes Active (high-speed, medium-speed) Operating mode mode or subactive mode tcyc tsubcyc tcyc tsubcyc Standby mode or watch mode Wait for oscActive (high-speed, medium-speed) illation mode or subactive mode stabilization tcyc tsubcyc tcyc tsubcyc φ or φSUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signal Figure 6.
Section 7 ROM Section 7 ROM The features of the 128-Kbyte flash memory built into the flash memory (F-ZTAT) version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 Kbyte × 4 blocks, 28 Kbytes × 1 block, 16 Kbytes × 1 block, 8 Kbytes × 2 blocks, and 32 Kbytes × 2 blocks. To erase the entire flash memory, each block must be erased in turn.
Section 7 ROM 7.1 Block Configuration Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 128-Kbyte flash memory is divided into 1 Kbyte × 4 blocks, 28 Kbytes × 1 block, 16 Kbytes × 1 block, 8 Kbytes × 2 blocks, and 32 Kbytes × 2 blocks . Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Erase block register 2 (EBR2) • Flash memory power control register (FLPWCR) • Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode.
Section 7 ROM Bit Bit Name Initial Value R/W Description 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE=1 and ESU=1, the flash memory changes to erase mode.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 is a register that is used to specify the flash memory erase area block. EBR1 is initialized to H'00 when the SWE1 bit in FLMCR1 is 0. Do not set more than one bit in EBR1 and EBR2 to 1 at a time, or this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 8 Kbytes of EB7 (H'00E000 to H'00FFFF) will be erased.
Section 7 ROM 7.2.4 Erase Block Register 2 (EBR2) EBR2 is a register that is used to specify the flash memory erase area block. EBR2 is initialized to H'00 when the SWE1 bit in FLMCR1 is 0. Do not set more than one bit in EBR1 and EBR2 to 1 at a time, or this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 to 2 All 0 R/(W) Reserved The initial value should not be changed.
Section 7 ROM 7.2.6 Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, EBR2, and FLPWCR. Bit Bit Name Initial Value R/W Description 7 FLSHE 0 R/W Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 All 0 Reserved These bits are always read as 0.
Section 7 ROM Table 7.1 TEST Setting Programming Modes NMI P36 PB0 PB1 PB2 LSI State after Reset End 0 1 x x x x User mode 0 0 1 x x x Boot mode 1 x x 0 0 0 Programmer mode [Legend] x: Don't care 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand.
Section 7 ROM 6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of program data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program.
Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . .
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps 8 to 10 MHz 4,800 bps 4 to 10 MHz 2,400 bps 2 to 10 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
Section 7 ROM 7.4 Using RAM to Emulate Flash Memory To use on-chip RAM in the realtime emulation of data to be written to the flash memory, the onchip RAM area can be overlaid on several blocks of flash memory (the emulation area). Figure 7.3 shows an example where an area of on-chip RAM is overlaid on the emulation area of the flash memory. 1. The area of on-chip RAM area to be overlaid on the emulation area (i.e. the overlay RAM area) is fixed to the 256 bytes from H'FFFC00 to H'FFFCFF. 2.
Section 7 ROM H'000000 Flash memory emulation area (H'000000 to H'0000FF) 256 bytes On-chip RAM (shadow of H'FFFC00 to H'FFFCFF) 256 bytes Flash memory Not used On-chip RAM overlay area 256 bytes On-chip RAM overlay area 256 bytes Normal memory map Memory map with overlaid RAM area H'0000FF H'020000 H'FFFC00 H'FFFCFF Figure 7.3 Address Map of Overlaid RAM Area Rev. 2.00 Jul.
Section 7 ROM 7.5 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 1 1 1 Remains in erased state Table 7.
Section 7 ROM 7.5.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.5 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1 (EBR1) or the erase block register 2 (EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 0 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data Verify data = all '1'? Increment address No Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes No Yes SWE bit ← 0 SWE bit ←
Section 7 ROM 7.6 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Section 7 ROM The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a reset. 7.
Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial Value) PDWND = 1 Active mode Normal operating mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Subsleep mode Standby mode Standby mode Module standby mode* Standby mode Standby mode Standby mode Standby mode Standby mode Note: * 7.
Section 7 ROM Transfer execution program to RAM (user area) Clear corresponding bit in interrupt enable register to 0 Set I bit in CCR to 1 Jump to address of execution program in RAM Clear FROMCKSTP bit in CRSTPR1 to 0 Figure 7.
Section 8 RAM Section 8 RAM Microcontrollers of the H8/38099 Group include an on-chip high-speed static RAM. The RAM is connected to the CPU via a 16-bit data bus, enabling two-cycle access by the CPU to both byte and word data. Product Classification RAM Size RAM Address Ranges Flash memory version H8/38099F 4 Kbytes H'FFCF80 to H'FFD37F, H'FFF380 to H'FFFF7F Masked ROM version H8/38099 4 Kbytes H'FFCF80 to H'FFD37F, H'FFF380 to H'FFFF7F H8/38098 2 Kbytes H'FFF780 to H'FFFF7F Rev. 2.00 Jul.
Section 8 RAM Rev. 2.00 Jul.
Section 9 I/O Ports Section 9 I/O Ports Microcontrollers of the H8/38099 Group incorporate 75 general I/O ports and eight general inputonly ports. Port 9 is a large current port, which can drive 15 mA (@VOL = 1.0 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
Section 9 I/O Ports 9.1.1 Port Data Register 1 (PDR1) PDR1 is a register that stores data of port 1. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1 and cannot be modified. 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W 9.1.2 Port Control Register 1 (PCR1) If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states.
Section 9 I/O Ports 9.1.3 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS of the port 1 pins in bit units. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1 and cannot be modified. 6 PUCR16 0 R/W 5 PUCR15 0 R/W 4 PUCR14 0 R/W 3 PUCR13 0 R/W 2 PUCR12 0 R/W 1 PUCR11 0 R/W 0 PUCR10 0 R/W 9.1.
Section 9 I/O Ports 9.1.5 Pin Functions The relationship between the register settings and the port functions is shown below. • P16/SCK4 pin Register Name Bit Name Setting Value SCSR4* CKS3* 1* 1 1 1 PCR1 1 CKS2 to CKS0* Other than B'111* B'111* 0* 1 x* 1 1 PCR16 1 0 P16 input pin 1 P16 output pin x SCK4 input pin* x SCK4 output pin* [Legend] x: Don't care TM Notes: 1. Supported only by the F-ZTAT version. 2. Only port function is available for the masked ROM version. Rev. 2.
Section 9 I/O Ports • P15/TIOCB2 pin Register Name TMDR_2 TIOR_2 TCR_2 PCR1 Bit Name MD1, MD0 IOB3 to IOB0 CCLR1, CCLR0 PCR15 B'00 B'0x00 B'xx 0 P15 input pin 1 P15 output pin 0 P15 input/TIOCB2 input pin 1 P15 output/TIOCB2 input pin x TIOCB2 output pin Setting Value B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'01 B'xxxx B'10 B'11 B'xx00 Other than B'xx00 B'10 Other than B'10 Pin Function 0 P15 input pin 1 P15 output pin 0 P15 input pin 1 P15 output pin 0 P15 inpu
Section 9 I/O Ports • P14/TIOCA2/TCLKC pin Register Name TMDR_2 TIOR_2 TCR_2 PCR1 Bit Name MD1, MD0 IOA3 to IOA0 CCLR1, CCLR0 PCR14 Setting Value B'00 B'0x00 B'xx 0 P14 input pin/ TCLKC*1 input pin 1 P14 output pin/ TCLKC*1 input pin 0 P14 input pin/TIOCA2/ TCLKC*1 input pin 1 P14 output pin/TIOCA2/ TCLKC*1 input pin B'0001 to B'0011, B'0101 to B'0111 x TIOCA2 output pin*2/ TCLKC*1 input pin B'xxxx 0 P14 input pin/TCLKC*1 input pin 1 P14 output pin/TCLKC*1 input pin 0 P14 inp
Section 9 I/O Ports • P13/TIOCB1/TCLKB pin Register Name TMDR_1 TIOR_1 TCR_1 PCR1 Bit Name MD1, MD0 IOB3 to IOB0 CCLR1, CCLR0 PCR13 Setting Value B'00 B'0x00 B'xx 0 P13 input pin/TCLKB* input pin 1 P13 output pin/TCLKB* input pin 0 P13 input pin/TIOCB1/TCLKB* input pin 1 P13 output pin/TIOCB1/TCLKB* input pin B'0001 to B'0011, B'0101 to B'0111 x TIOCB1 output pin/TCLKB* input pin B'xxxx 0 P13 input pin/TCLKB* input pin 1 P13 output pin/TCLKB* input pin 0 P13 input pin/TCLKB*
Section 9 I/O Ports • P12/TIOCA1/TCLKA pin Register Name TMDR_1 TIOR_1 TCR_1 PCR1 Bit Name MD1, MD0 IOA3 to IOA0 CCLR1, CCLR0 PCR12 B'00 B'0x00 B'xx 0 P12 input pin/TCLKA*1 input pin 1 P12 output pin/TCLKA*1 input pin 0 P12 input pin/TIOCA1/TCLKA*1 input pin 1 P12 output pin/TIOCA1/TCLKA*1 input pin B'0001 to B'0011, B'0101 to B'0111 x TIOCA1 output pin*2/TCLKA*1 input pin B'xxxx 0 P12 input pin/TCLKA*1 input pin 1 P12 output pin/TCLKA*1 input pin 0 P12 input pin/TCLKA*1 input
Section 9 I/O Ports • P11/AEVL pin Register Name PMR1 PCR1 Bit Name AEVL PCR11 0 0 P11 input pin 1 P11 output pin 1 x AEVL input pin Register Name PMR1 PCR1 Pin Function Bit Name AEVH PCR10 0 0 P10 input pin 1 P10 output pin x AEVH input pin Setting Value Pin Function [Legend] x: Don't care • P10/AEVH pin Setting Value 1 [Legend] x: Don't care 9.1.6 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software.
Section 9 I/O Ports 9.2 Port 3 Port 3 is an I/O port; its pins can also be configured to function as an SCI4 I/O pin, SCI3_2 I/O pin, IIC2 I/O pin, and RTC output pin. Figure 9.2 shows the pin configuration. P37/SO4 Port 3 P36/SI4 P32/TXD32/SCL P31/RXD32/SDA P30/SCK32/TMOW/CLKOUT Figure 9.2 Port 3 Pin Configuration Port 3 has the following registers. • Port data register 3 (PDR3) • Port control register 3 (PCR3) • Port pull-up control register 3 (PUCR3) • Port mode register 3 (PMR3) 9.2.
Section 9 I/O Ports 9.2.2 Port Control Register 3 (PCR3) PCR3 selects inputs/outputs in bit units for pins of port 3. Bit Bit Name Initial Value R/W Description 7 PCR37 0 W 6 PCR36 0 W Setting a PCR3 bit to 1 makes the corresponding pin (P37 or P36) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid when the corresponding pin is designated as a general I/O pin. PCR3 is a write-only register. These bits are always read as 1.
Section 9 I/O Ports 9.2.3 Port Pull-Up Control Register 3 (PUCR3) PUCR3 controls the pull-up MOS of port 3 pins in bit units. Bit Bit Name Initial Value R/W Description 7 PUCR37 0 R/W 6 PUCR36 0 R/W When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. 5 to 1 All 1 Reserved These bits are always read as 1 and cannot be modified. 0 PUCR30 0 R/W 9.2.
Section 9 I/O Ports 9.2.5 Pin Functions The relationship between the register settings and the port functions is shown below. • P37/SO4 pin Register Name Bit Name Setting Value SCR4* TE* 0* 1 1* 1 1 1 PCR3 Pin Function PCR37 0 P37 input pin 1 P37 output pin x SO4 output pin* 2 [Legend] x: Don't care TM Notes: 1. Supported only by the F-ZTAT version. 2. Only port function is available for the masked ROM version.
Section 9 I/O Ports • P32/TXD32/SCL pin Register Name Bit Name Setting Value ICCR1 PFCR SPCR PCR3 ICE SC32S SPC32 PCR32 0 0 0 0 P32 input pin 1 P32 output pin 1 x TXD32 output pin x 0 P32 input pin 1 P32 output pin x SCL I/O pin Pin Function 1 1 x Pin Function [Legend] x: Don't care • P31/RXD32/SDA pin Register Name Bit Name Setting Value ICCR1 PFCR SCR3_2 PCR3 ICE SC32S RE PCR31 0 0 0 0 P31 input pin 1 P31 output pin 1 x RXD32 input pin x 0 P31 input pi
Section 9 I/O Ports • P30/SCK32/TMOW/CLKOUT pin Register PMR3 PFCR SMR3_2 SCR3_2 PCR3 Pin Function Name Bit Name Setting TMOW CLKOUT1 CLKOUT0 0 x x SC32S COM CKE1 CKE0 PCR30 0 0 0 0 0 Value 1 1 0 1 1 1 1 0 1 0 x x x P30 input pin 1 P30 output pin x SCK32 output pin 0 SCK32 input pin 1 Setting prohibited 0 SCK32 output pin 1 Setting prohibited 0 SCK32 input pin 1 Setting prohibited x 0 P30 input pin 1 P30 output pin x CLKOUT output pin (φOSC) 1 CLK
Section 9 I/O Ports 9.3 Port 4 Port 4 is an I/O port; its pins can also be configured to function as SCI3_1 I/O pins and timer F I/O pins. Figure 9.3 shows its pin configuration. Port 4 P42/TXD31/IrTXD/TMOFH P41/RXD31/IrRXD/TMOFL P40/SCK31/TMIF Figure 9.3 Port 4 Pin Configuration Port 4 has the following registers. • Port data register 4 (PDR4) • Port control register 4 (PCR4) • Port mode register 4 (PMR4) 9.3.1 Port Data Register 4 (PDR4) PDR4 is a register that stores data of port 4.
Section 9 I/O Ports 9.3.2 Port Control Register 4 (PCR4) PCR4 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 4. Bit Bit Name Initial Value R/W Description 7 to 3 All 1 Reserved These bits are always read as 1 and cannot be modified. 2 PCR42 0 W 1 PCR41 0 W 0 PCR40 0 W Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Section 9 I/O Ports 9.3.3 Port Mode Register 4 (PMR4) PMR4 controls the selection of functions for port 4 pins. Bit Bit Name Initial Value R/W Description 7 to 3 All 1 Reserved These bits are always read as 1 and cannot be modified. 2 TMOFH 0 R/W P42/TXD31/IrTXD/TMOFH Pin Function Switch Selects whether pin P42/TXD31/IrTXD/TMOFH is used as P42 or TXD31/IrTXD, or as TMOFH.
Section 9 I/O Ports 9.3.4 Pin Functions The relationship between the register settings and the port functions is shown below.
Section 9 I/O Ports • P40/SCK31/TMIF pin Register Name PMR4 PFCR SMR3_1 Bit Name TMIF SC31S COM CKE1 CKE0 PCR40 0 0 0 0 0 0 Setting Value SCR3_1 PCR4 1 1 1 0 1 1 1 x x Pin Function P40 input pin 1 P40 output pin x SCK31 output pin 0 SCK31 input pin 1 Setting prohibited 0 SCK31 output pin 1 Setting prohibited 0 SCK31 input pin 1 Setting prohibited x x 0 P40 input pin 1 P40 output pin x TMIF input pin [Legend] x: Don't care 9.
Section 9 I/O Ports Port 5 has the following registers. • Port data register 5 (PDR5) • Port control register 5 (PCR5) • Port pull-up control register 5 (PUCR5) • Port mode register 5 (PMR5) 9.4.1 Port Data Register 5 (PDR5) PDR5 is a register that stores data of port 5. Bit Bit Name Initial Value R/W Description 7 P57 0 R/W 6 P56 0 R/W 5 P55 0 R/W If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states.
Section 9 I/O Ports 9.4.3 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS of the port 5 pins in bit units. Bit Bit Name Initial Value R/W Description 7 PUCR57 0 R/W 6 PUCR56 0 R/W 5 PUCR55 0 R/W When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
Section 9 I/O Ports 9.4.5 Pin Functions The relationship between the register settings and the port functions is shown below.
Section 9 I/O Ports 9.4.6 Input Pull-Up MOS Port 5 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset. (n = 7 to 0) PCR5n 0 1 PUCR5n 0 1 x Input Pull-Up MOS Off On Off [Legend] x: Don't care 9.
Section 9 I/O Ports 9.5.1 Port Data Register 6 (PDR6) PDR6 is a register that stores data of port 6. Bit Bit Name Initial Value R/W Description 7 P67 0 R/W 6 P66 0 R/W 5 P65 0 R/W If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read. 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W 9.5.
Section 9 I/O Ports 9.5.3 Port Pull-Up Control Register 6 (PUCR6) PUCR6 controls the pull-up MOS of the port 6 pins in bit units. Bit Bit Name Initial Value R/W Description 7 PUCR67 0 R/W 6 PUCR66 0 R/W 5 PUCR65 0 R/W When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
Section 9 I/O Ports • P63/SEG12 to P60/SEG9 pins (m = 3 to 0) Register Name LPCR PCR6 Bit Name SGS3 to SGS0 PCR6m B'000x, B'0010, B'1011, B'11xx 0 P6m input pin 1 P6m output pin Other than B'000x, B'0010, B'1011, B'11xx x SEGm+9 output pin Setting Value Pin Function [Legend] x: Don't care 9.5.5 Input Pull-Up MOS Port 6 has an on-chip input pull-up MOS function that can be controlled by software.
Section 9 I/O Ports 9.6 Port 7 Port 7 is an I/O pins; its pins can also be configured to function as LCD segment output pins. Figure 9.6 shows the pin configuration. P77/SEG24 P76/SEG23 Port 7 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 Figure 9.6 Port 7 Pin Configuration Port 7 has the following registers. • Port data register 7 (PDR7) • Port control register 7 (PCR7) 9.6.1 Port Data Register 7 (PDR7) PDR7 is a register that stores data of port 7.
Section 9 I/O Ports 9.6.2 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins of port 7. Bit Bit Name Initial Value R/W Description 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR7 and in PDR7 are valid when the corresponding pin is designated as a general I/O pin.
Section 9 I/O Ports • P73/SEG20 to P70/SEG17 pins (m = 3 to 0) Register Name LPCR PCR7 Bit Name SGS3 to SGS0 PCR7m B'00xx, B'0100, B'1101, B'111x 0 P7m input pin 1 P7m output pin Other than B'00xx, B'0100, B'1101, B'111x x SEGm+17 output pin Setting Value Pin Function [Legend] x: Don't care 9.7 Port 8 Port 8 is an I/O pins; its pins can also be configured to function as LCD segment output pins. Figure 9.7 shows the pin configuration.
Section 9 I/O Ports 9.7.1 Port Data Register 8 (PDR8) PDR8 is a register that stores data of port 8. Bit Bit Name Initial Value R/W Description 7 P87 0 R/W 6 P86 0 R/W 5 P85 0 R/W If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. 4 P84 0 R/W 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P80 0 R/W 9.7.
Section 9 I/O Ports 9.7.3 Pin Functions The relationship between the register settings and the port functions is shown below.
Section 9 I/O Ports 9.8 Port 9 Port 9 is a general I/O port; its pins can also be configured to function as an external interrupt input pin and PWM output pins. Figure 9.8 shows the pin configuration. P93/PWM4 Port 9 P92/PWM3/IRQ4 P91/PWM2 P90/PWM1 Figure 9.8 Port 9 Pin Configuration Port 9 has the following registers. • Port data register 9 (PDR9) • Port control register 9 (PCR9) • Port mode register 9 (PMR9) 9.8.1 Port Data Register 9 (PDR9) PDR9 is a register that stores data of port 9.
Section 9 I/O Ports 9.8.2 Port Control Register 9 (PCR9) PCR9 selects inputs/outputs in bit units for pins of port 9. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1 and cannot be modified. 3 PCR93 0 W 2 PCR92 0 W 1 PCR91 0 W 0 PCR90 0 W Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Section 9 I/O Ports Bit Bit Name Initial Value R/W Description 1 PWM2 0 R/W P9n/PWMn+1 Pin Function Switch 0 PWM1 0 R/W Select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1. (n = 1, 0) 0: P9n I/O pin 1: PWMn+1 output pin 9.8.4 Pin Functions The relationship between the register settings and the port functions is shown below.
Section 9 I/O Ports • P91/PWM2 and P90/PWM1 pins (n = 1, 0) Register Name Bit Name Setting Value PMR9 PCR9 PWMn+1 PCR9n 0 0 P9n input pin 1 P9n output pin x PWMn+1 output pin 1 Pin Function [Legend] x: Don't care 9.9 Port A Port A is an I/O pins; its pins can also be configured to function as LCD common output pins. Figure 9.9 shows the pin configuration. Port A PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 Figure 9.9 Port A Pin Configuration Port A has the following registers.
Section 9 I/O Ports 9.9.1 Port Data Register A (PDRA) PDRA is a register that stores data of port A. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1 and cannot be modified. 3 PA3 0 R/W 2 PA2 0 R/W 1 PA1 0 R/W 0 PA0 0 R/W 9.9.2 Port Control Register A (PCRA) If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states.
Section 9 I/O Ports 9.9.3 Pin Functions The relationship between the register settings and the port functions is shown below.
Section 9 I/O Ports • PA1/COM2 pin Register Name Bit Name Setting Value LPCR PCRA Pin Function SGS3 to SGS0 DTS1, DTS0, CMX PCRA1 B'0000 x 0 PA1 input pin 1 PA1 output pin 0 PA1 input pin Other than B'0000 B'000 Other than B'000 1 PA1 output pin x COM2 output pin [Legend] x: Don't care • PA0/COM1 pin Register Name Bit Name Setting Value LPCR PCRA SGS3 to SGS0 PCRA0 B'0000 0 PA0 input pin 1 PA0 output pin x COM1 output pin Other than B'0000 Pin Function [Legend] x: Don't
Section 9 I/O Ports 9.10 Port B Port B is an input-only port: its pins can also be configured to function as an interrupt input pin and analog input pin. Figure 9.10 shows the pin configuration. PB7/AN7 PB6/AN6 Port B PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2/IRQ3 PB1/AN1/IRQ1 PB0/AN0/IRQ0 Figure 9.10 Port B Pin Configuration Port B has the following registers. • Port data register B (PDRB) • Port mode register B (PMRB) 9.10.1 Port Data Register B (PDRB) PDRB is a register that stores data of port B.
Section 9 I/O Ports 9.10.2 Port Mode Register B (PMRB) PMRB controls the selection of the port B pin functions. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1 and cannot be modified. 4 ADTSTCHG 0 R/W TEST/ADTRG Pin Function Switch Selects whether pin TEST/ADTRG is used as TEST or as ADTRG. 0: TEST pin 1: ADTRG input pin For details on the setting of the ADTRG input pin, refer to section 20.4.2, External Trigger Input Timing.
Section 9 I/O Ports 9.10.3 Pin Functions The relationship between the register settings and the port functions is shown below.
Section 9 I/O Ports • PB3/AN3 pin Register Name AMR Bit Name Pin Function CH3 to CH0 Setting Value Other than B'0111 PB3 input pin B'0111 AN3 input pin • PB2/AN2/IRQ3 pin Register Name PMRB AMR Bit Name IRQ3 CH3 to CH0 0 Other than B'0110 PB2 input pin B'0110 AN2 input pin Other than B'0110 IRQ3 input pin B'0110 Setting prohibited Pin Function Setting Value 1 Pin Function • PB1/AN1/IRQ1 pin Register Name PMRB AMR Bit Name IRQ1 CH3 to CH0 0 Other than B'0101 PB1 input pi
Section 9 I/O Ports 9.11 Port C Port C is an I/O port; its pins can also be configured to function as LCD segment output pins. Figure 9.11 shows the pin configuration. PC7/SEG40 PC6/SEG39 Port C PC5/SEG38 PC4/SEG37 PC3/SEG36 PC2/SEG35 PC1/SEG34 PC0/SEG33 Figure 9.11 Port C Pin Configuration Port C has the following registers. • Port data register C (PDRC) • Port control register C (PCRC) 9.11.1 Port Data Register C (PDRC) PDRC is a register that stores data of port C.
Section 9 I/O Ports 9.11.2 Port Control Register C (PCRC) PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C. Bit Bit Name Initial Value R/W Description 7 PCRC7 0 W 6 PCRC6 0 W 5 PCRC5 0 W Setting a PCRC bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. 4 PCRC4 0 W 3 PCRC3 0 W 2 PCRC2 0 W 1 PCRC1 0 W 0 PCRC0 0 W 9.11.3 Pin Functions PCRC is a write-only register.
Section 9 I/O Ports 9.12 Port E Port E is an I/O port; its pins can also be configured to function as external interrupt input pins, SCI3_2 I/O pins, SCI3_3 I/O pins, and timer C input pin. Figure 9.12 shows its pin configuration. PE7/TMIC(/IRQ0) PE6/UD Port E PE5(/TXD32) PE4(/RXD32) PE3(/SCK32/IRQ1) PE2/TXD33 PE1/RXD33 PE0/SCK33(/IRQ3) Figure 9.12 Port E Pin Configuration Port E has the following registers.
Section 9 I/O Ports 9.12.2 Port Control Register E (PCRE) PCRE selects inputs/outputs in bit units for pins of port E. Bit Bit Name Initial Value R/W Description 7 PCRE7 0 W 6 PCRE6 0 W 5 PCRE5 0 W 4 PCRE4 0 W Setting a PCRE bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCRE and in PDRE are valid when the corresponding pin is designated as a general I/O pin.
Section 9 I/O Ports Bit Bit Name Initial Value R/W Description 0 IRQ3 0 R/W PE0/IRQ3 Pin Function Switch 0: PE0 I/O pin 1: IRQ3 input pin 9.12.4 Pin Functions The relationship between the register settings and the port functions is shown below.
Section 9 I/O Ports • PE5 (/TXD32) pin Register Name PFCR SPCR PCRE Bit Name SC32S SPC32 PCRE5 0 x 0 PE5 input pin 1 PE5 output pin 0 PE5 input pin Setting Value 1 0 Pin Function 1 PE5 output pin 1 x TXD32 output pin Pin Function [Legend] x: Don't care • PE4 (/RXD32) pin Register Name PFCR SCR3_2 PCRE Bit Name SC32S RE PCRE4 0 x 0 PE4 input pin 1 PE4 output pin 0 PE4 input pin 1 PE4 output pin x RXD32 input pin Setting Value 1 0 1 [Legend] x: Don't care Re
Section 9 I/O Ports • PE3 (/SCK32/IRQ1) pin Register Name PMRB PMRE PFCR SMR3_2 Bit Name IRQ1 IRQ1 SC32S COM CKE1 CKE0 PCRE3 0 1 x x x x x 0 x x x 0 PE3 input pin 1 PE3 output pin 0 PE3 input pin 1 PE3 output pin x SCK32 output pin Setting Value Other than above 1 0 SCR3_2 0 PCRE 0 1 1 0 1 1 Pin Function IRQ1 input pin 0 SCK32 input pin 1 Setting prohibited 0 SCK32 output pin 1 Setting prohibited 0 SCK32 input pin 1 Setting prohibited [Legend] x:
Section 9 I/O Ports • PE1/RXD33 pin Register Name Bit Name SCR3_3 PCRE RE PCRE1 0 0 PE1 input pin 1 PE1 output pin x RXD33 input pin Setting Value 1 Pin Function [Legend] x: Don't care • PE0/SCK33 (/IRQ3) pin PMRB PMRE SMR3_3 Bit Name IRQ3 IRQ3 COM CKE1 CKE0 PCRE0 0 1 x x x x IRQ3 input pin 0 0 0 0 PE0 input pin 1 PE0 output pin x SCK33 output pin Setting Value Other than above SCR3_3 PCRE Pin Function Register Name 1 1 1 0 1 Setting prohibited 0 0 SCK
Section 9 I/O Ports 9.13 Port F Port F is an I/O port: its pins can also be configured to function as an external interrupt input pin, SCI3_1 I/O pins, and timer G input pin. Figure 9.13 shows the pin configuration. Port F PF3(/TXD31/IrTXD) PF2(/RXD31/IrRXD) PF1(/SCK31/IRQ4) PF0/TMIG Figure 9.13 Port F Pin Configuration Port F has the following registers. • Port data register F (PDRF) • Port control register F (PCRF) • Port mode register F (PMRF) 9.13.
Section 9 I/O Ports 9.13.2 Port Control Register F (PCRF) PCRF selects inputs/outputs in bit units for pins of port F. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1 and cannot be modified. 4 Reserved The write value should always be 0. 3 PCRF3 0 W 2 PCRF2 0 W 1 PCRF1 0 W 0 PCRF0 0 W Setting a PCRF bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Section 9 I/O Ports 9.13.4 Pin Functions The relationship between the register settings and the port functions is shown below.
Section 9 I/O Ports • PF1 (/SCK31/IRQ4) pin Register Name PMR9 PMRF PFCR SMR3_1 Bit Name IRQ4 IRQ4 SC31S COM CKE1 CKE0 PCRF1 0 1 x x x x x 0 x x x 0 PF1 input pin 1 PF1 output pin 0 PF1 input pin 1 PF1 output pin x SCK31 output pin Setting Value Other than above 0 1 SCR3_1 0 PCRF 0 1 1 1 0 1 Pin Function IRQ4 input pin 0 SCK31 input pin 1 Setting prohibited 0 SCK31 output pin 1 Setting prohibited 0 SCK31 input pin 1 Setting prohibited [Legend] x:
Section 9 I/O Ports 9.14 Input/Output Data Inversion 9.14.1 Serial Port Control Register, Serial Port Control Register 2 (SPCR, SPCR2) SPCR switches input/output data inversion of the RXD (IrRXD) and TXD (IrTXD) pins. Figure 9.14 shows a input/output data inversion function.
Section 9 I/O Ports Bit Bit Name Initial Value R/W Description 4 SPC31 0 R/W P42/TXD31/IrTXD/TMOFH (PF3/TXD31/IrTXD) Pin Function Switch Selects whether pin P42/TXD31/IrTXD/TMOFH (PF3/TXD31/IrTXD) is used as P42/TMOFH (PF3) or as TXD31/IrTXD. 0: P42 (PF3) I/O pin or TMOFH output pin 1: TXD31/IrTXD output pin* Note: Set the TE bit in SCR3_1 after having set this bit to 1.
Section 9 I/O Ports • SPCR2 Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1 and cannot be modified. 4 SPC33 0 R/W PE2/TXD33 Pin Function Switch Selects whether pin PE2/TXD33 is used as PE2 or as TXD33. 0: PE2 I/O pin 1: TXD33 output pin Set the TE bit in SCR3_3 after having set this bit to 1. 3 1 Reserved 2 1 These bits are always read as 1 and cannot be modified.
Section 9 I/O Ports 9.15 Port Function Switch 9.15.1 Port Function Control Register (PFCR) PFCR controls the assignments of pins for SCI3_1 and SCI3_2 and the functions of other pins. Initial Value R/W Description CLKOUT1 1 R/W TMOW/CLKOUT Pin Function Switch CLKOUT0 1 R/W 00: CLKOUT output pin (φOSC) Bit Bit Name 7 6 01: CLKOUT output pin (φOSC/2) 10: CLKOUT output pin (φOSC/4) 11: TMOW output pin 5 1 Reserved This bit is always read as 1 and cannot be modified.
Section 9 I/O Ports Bit Bit Name Initial Value R/W Description 0 SC31S 0 R/W SCI3_1 Pin Assignment Select 0: TXD31 is assigned to P42 RXD31 is assigned to P41 SCK31 is assigned to P40 1: TXD31 is assigned to PF3 RXD31 is assigned to PF2 SCK31 is assigned to PF1 9.16 Usage Notes 9.16.1 How to Handle Unused Pin If an I/O pin not used by the user system is floating, pull it up or down.
Section 10 Realtime Clock (RTC) Section 10 Realtime Clock (RTC) The realtime clock (RTC) is a timer used to count periods of time ranging from a second to a week. Interrupts can be generated at intervals ranging from 0.25 seconds to a week. Figure 10.1 is a block diagram of the RTC. 10.1 Features • Counts seconds, minutes, hours, and day-of-week • Start/stop function • Reset function • Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes • Periodic (0.25 seconds, 0.
Section 10 Realtime Clock (RTC) 10.2 Input/Output Pin Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration Pin Name Abbreviation I/O Function Clock output TMOW Output RTC divided clock output 10.3 Register Descriptions The RTC has the following registers.
Section 10 Realtime Clock (RTC) 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit read register used as a counter, when it operates as a free running counter. For more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, Data Reading Procedure.
Section 10 Realtime Clock (RTC) 10.3.2 Minute Data Register (RMINDR) RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59. Bit Bit Name Initial Value R/W Description 7 BSY —/(0)* R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.3 Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1. Bit Bit Name Initial Value R/W Description 7 BSY —/(0)* R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0. Bit Bit Name Initial Value R/W Description 7 BSY —/(0)* R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.5 RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2. Bit Bit Name Initial Value R/W Description 7 RUN —/(0)* R/W RTC Operation Start 0: Stops RTC operation 1: Starts RTC operation 6 12/24 —/(0)* R/W Operating Mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode. RHRDR counts on 0 to 23. 5 PM —/(0)* R/W A.m./P.m.
Section 10 Realtime Clock (RTC) Noon 24-hour count 0 12-hour count 0 PM 1 1 2 2 3 3 4 4 5 6 7 5 6 7 0 (Morning) 8 8 9 10 11 12 13 14 15 16 17 9 10 11 0 1 2 3 4 5 1 (Afternoon) 24-hour count 18 19 20 21 22 23 0 12-hour count 6 7 8 9 10 11 0 1 (Afternoon) 0 PM Figure 10.2 Definition of Time Expression Rev. 2.00 Jul.
Section 10 Realtime Clock (RTC) 10.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds. Enabling interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds sets the corresponding flag to 1 in the RTC interrupt flag register (RTCFLG) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter.
Section 10 Realtime Clock (RTC) 10.3.7 Clock Source Select Register (RTCCSR) RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than φw/4 is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read.
Section 10 Realtime Clock (RTC) 10.3.8 RTC Interrupt Flag Register (RTCFLG) RTCFLG sets the corresponding flag when an interrupt occurs. Each flag is not cleared automatically even if the interrupt is accepted. To clear the flag, 0 should be written to the flag.
Section 10 Realtime Clock (RTC) 10.4 Operation 10.4.1 Initial Settings of Registers after Power-On The RTC registers that store second, minute, hour, and day-of-week data, control registers, and interrupt registers are not initialized by a RES input, or by a reset source caused by a watchdog timer. Therefore, all registers must be set to their initial values after power-on. Once the register settings are made, the RTC provides an accurate time as long as power is supplied regardless of a RES input. 10.
Section 10 Realtime Clock (RTC) 10.4.3 Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1.
Section 10 Realtime Clock (RTC) 10.5 Interrupt Sources There are eight kinds of RTC interrupts: a free-running counter overflow, week interrupt, day interrupt, hour interrupt, minute interrupt, one-second interrupt, 0.5-second interrupt, and 0.25second interrupt. When using an interrupt, set the IENRTC (RTC interrupt request enable) bit in IENR1 to 1 last after other registers are set. When an interrupt request of the RTC occurs, the corresponding flag in RTCFLG is set to 1.
Section 10 Realtime Clock (RTC) 10.6 Usage Notes 10.6.1 Note on Clock Count The subclock must be connected to the 32.768-kHz resonator. When the 38.4-kHz resonator etc. is connected, the correct time count is not possible. 10.6.2 Note when Using RTC Interrupts The RTC registers are not reset by a RES input, power-on, or overflow of the watchdog timer, and their values are undefined after power-on.
Section 10 Realtime Clock (RTC) Rev. 2.00 Jul.
Section 11 Timer C Section 11 Timer C Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 11.1 Features Features of timer C are given below. • Choice of nine internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φW/4, φW/256, and φW/1024) or an external clock (can be used to count external events). • An interrupt is requested when the counter overflows.
Section 11 Timer C 11.2 Input/Output Pins Table 11.1 shows the input/output pins of the timer C. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer C event input TMIC Input Input pin for event input to TCC Timer C up/down select UD Input Timer C up/down-count selection 11.3 Register Descriptions Timer C has the following registers. For details on clock halt register 3 (CKSTPR3), see section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3).
Section 11 Timer C 11.3.1 Timer Mode Register C (TMC) TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and performing up/down-counter control. Upon reset, TMC is initialized to H'10. Bit Bit Name Initial Value R/W Description 7 TMC7 0 R/W Auto-Reload Function Select Selects whether timer C is used as an interval timer or auto-reload timer.
Section 11 Timer C Bit Bit Name Initial Value 3 2 1 0 TMC3 TMC2 TMC1 TMC0 0 0 0 0 R/W Description R/W Clock Select TMC3 to TMC0 select the clock input for TCC. For the counting of external events, either the rising or falling edge can be selected.
Section 11 Timer C 11.3.2 Timer Counter C (TCC) TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC3 to TMC0 in the timer mode register C (TMC). TCC values can be read by the CPU at any time. When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.
Section 11 Timer C 11.4 Timer Operation 11.4.1 Interval Timer Operation When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, TCC is initialized to H'00 and TMC to H'10, so TCC continues up-counting as an interval up-counter without halting immediately after a reset. The timer C operating clock is selected from nine internal clock signals output by prescalers S and W, or an external clock input at pin TMIC.
Section 11 Timer C 11.4.2 Auto-Reload Timer Operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that value.
Section 11 Timer C 11.5 Timer C Operation States Table 11.2 summarizes the timer C operation states. Table 11.
Section 12 Timer F Section 12 Timer F The timer F is a 16-bit timer having an output compare function. The timer F also provides for external event counting, and counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Thus, it can be applied to various systems. The timer F can also be used as two independent 8-bit timers (timer FH and timer FL). Figure 12.1 shows a block diagram of the timer F. 12.
Section 12 Timer F φ PSS IRRTFL TCRF φW/4 TMIF TCFL Toggle circuit Comparator Internal data bus TMOFL OCRFL TCFH Toggle circuit TMOFH Comparator [Legend] TCRF: TCSRF: TCFH: TCFL: OCRFH: OCRFL: IRRTFH: IRRTFL: PSS: OCRFH Timer control register F Timer control status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S TCSRF IRRTFH Figure 12.
Section 12 Timer F 12.3 Register Descriptions The timer F has the following registers. • Timer counters FH and FL (TCFH, TCFL) • Output compare registers FH and FL (OCRFH, OCRFL) • Timer control register F (TCRF) • Timer control/status register F (TCSRF) 12.3.1 Timer Counters FH and FL (TCFH, TCFL) TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL.
Section 12 Timer F 12.3.2 Output Compare Registers FH and FL (OCRFH, OCRFL) OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers. (1) 16-Bit Mode (OCRF) When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register.
Section 12 Timer F 12.3.3 Timer Control Register F (TCRF) TCRF switches between 16-bit mode and 8-bit mode, selects the input clock from among four counter input clock sources, and selects the output level of the TMOFH and TMOFL pins. Bit Bit Name Initial Value R/W Description 7 TOLH 0 W Toggle Output Level H Sets the TMOFH pin output level.
Section 12 Timer F Bit Bit Name Initial Value R/W Description 2 1 0 CKSL2 CKSL1 CKSL0 0 0 0 W W W Clock Select L Select the clock input to TCFL from among four internal clock sources or external event input.
Section 12 Timer F Bit Bit Name Initial Value R/W Description 5 OVIEH 0 R/W Timer Overflow Interrupt Enable H Selects enabling or disabling of interrupt generation when TCFH overflows. 0: TCFH overflow interrupt request is disabled 1: TCFH overflow interrupt request is enabled 4 CCLRH 0 R/W Counter Clear H In 16-bit mode, this bit selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, this bit selects whether TCFH is cleared when TCFH and OCRFH match.
Section 12 Timer F Bit Bit Name Initial Value R/W Description 1 OVIEL 0 R/W Timer Overflow Interrupt Enable L Selects enabling or disabling of interrupt generation when TCFL overflows. 0: TCFL overflow interrupt request is disabled 1: TCFL overflow interrupt request is enabled 0 CCLRL 0 R/W Counter Clear L Selects whether TCFL is cleared when TCFL and OCRFL match. 0: TCFL clearing by compare match is disabled 1: TCFL clearing by compare match is enabled Note: * 12.
Section 12 Timer F OCRF contents are constantly compared with TCF, and when both values satisfy the compare match condition, CMFH is set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU, and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared. The output level of the TMOFH pin can be set by the TOLH bit in TCRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF.
Section 12 Timer F 12.4.2 (1) TCF Increment Timing Internal Clock Operation TCF is incremented by internal clock or external event input. Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of internal clock sources (φ/32, φ/16, φ/4, or φW/4) created by dividing the system clock (φ or φW). φ Count input clock (φ/4) TCF N-1 N N+1 Figure 12.2 Count Timing for Internal Clock Operation (2) External Event Operation When the CKSL2 bit in TCRF is cleared to 0, external event input is selected.
Section 12 Timer F 12.4.3 TMOFH/TMOFL Output Timing In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is toggled by the occurrence of a compare match. Figure 12.4 shows the output timing. φ Count input clock (φ/4) N-1 TCF OCRF 0 N N Compere match signal TMOFH, TMOFL Figure 12.4 TMOFH/TMOFL Output Timing 12.4.4 TCF Clear Timing TCF can be cleared by a compare match with OCRF. φ Count input clock (φ/4) TCF OCRF N-1 N 0 N Compare match signal Figure 12.
Section 12 Timer F 12.4.5 Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. 12.4.6 Compare Match Flag Set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock.
Section 12 Timer F 12.5 Timer F Operating States The timer F operating states are shown in table 12.2. Table 12.
Section 12 Timer F 12.6 Usage Notes The following types of contention and operation can occur when the timer F is used. 12.6.1 16-Bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
Section 12 Timer F (2) TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid.
Section 12 Timer F The term of validity of "Interrupt source generation signal" = 1 cycle of φW + waiting time for completion of executing instruction + interrupt time synchronized with φ = 1/φW + ST × (1/φ) + (2/φ) (second).....(1) ST: Executing number of execution states Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2.
Section 12 Timer F Interrupt request flag clear 2 Program processing Interrupt Interrupt request flag clear Interrupt Normal φW Interrupt source generation signal (internal signal, nega-active) Overflow signal, compare match signal (internal signal, nega-active) Interrupt request flag (IRRTFH, IRRTFL) 1 Figure 12.7 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid 12.6.
Section 12 Timer F Rev. 2.00 Jul.
Section 13 Timer G Section 13 Timer G Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceller, enabling accurate measurement of the input capture input signal duty cycle. If input capture input is not set, timer G functions as an 8-bit interval timer. 13.
Section 13 Timer G φ PSS Level detector φW/4 ICRGF TMIG Noise canceler Edge detector NCS Internal data bus TMG TCG ICRGR IRRTG [Legend] TMG: TCG: ICRGF: ICRGR: IRRTG: NCS: PSS: Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer G interrupt request flag Noise canceler select Prescaler S Figure 13.1 Block Diagram of Timer G Rev. 2.00 Jul.
Section 13 Timer G 13.2 Input/Output Pins Table 13.1 shows the timer G pin configuration. Table 13.1 Pin Configuration Pin Name Abbreviation I/O Function Input capture input TMIG Input Input capture input pin 13.3 Register Descriptions The timer G has the following registers. For details on the clock halt register 3 (CKSTPR3), see section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3).
Section 13 Timer G 13.3.2 Input Capture Register GF (ICRGF) ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details on interrupts, see section 4, Interrupt Controller.
Section 13 Timer G Bit Bit Name Initial Value R/W 7 OVFH 0 R/(W)* Timer Overflow Flag H Description Indicates that TCG has overflowed from H'FF to H'00 when the input capture input signal is high. This flag is set by hardware and cleared by software. It cannot be set by software.
Section 13 Timer G Bit Bit Name Initial Value R/W Description 4 IIEGS 0 R/W Input Capture Interrupt Edge Select Selects the input capture input signal edge that generates an interrupt request.
Section 13 Timer G 13.3.5 Clock Halt Register 3 (CKSTPR3) For details on placing timer G in and taking it out of module standby mode (this is controlled by the TGCKSTP bit in CKSTPR3) see section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3). 13.4 Noise Canceller The noise canceller consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceller is set by NCS* in PMRF. Figure 13.
Section 13 Timer G The noise canceller consists of five latch circuits connected in series and a match detector circuit. When the noise cancellation function is not used (NCS = 0), the system clock is selected as the sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the rising edge of this clock, and the data is judged to be correct when all the latch outputs match.
Section 13 Timer G 13.5 Operation Timer G is an 8-bit timer with built-in input capture and interval functions. 13.5.1 Timer G Functions Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below. (1) Input Capture Timer Operation When the TMIG bit in the port mode register F (PMRF) is set to 1, timer G functions as an input capture timer*.
Section 13 Timer G (2) Interval Timer Operation When the TMIG bit in PMRF is cleared to 0, timer G functions as an interval timer. Following a reset, TCG starts counting on the φ/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit in TMG is set to 1.
Section 13 Timer G (2) With Noise Cancellation Function When noise cancellation is performed on the input capture input, the passage of the input capture signal through the noise canceller results in a delay of five sampling clock cycles from the input capture input signal edge. Figure 13.5 shows the timing in this case. Input capture input signal Sampling clock Noise canceler output Input capture signal R Figure 13.5 Input Capture Input Timing (with Noise Cancellation Function) 13.5.
Section 13 Timer G 13.5.5 TCG Clear Timing TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 13.7 shows the timing for clearing by both edges. φ Input capture input signal Input capture signal F Input capture signal R TCG N H'00 Figure 13.7 TCG Clear Timing Rev. 2.00 Jul.
Section 13 Timer G 13.6 Timer G Operation Modes Timer G operation modes are shown in table 13.2. Table 13.
Section 13 Timer G 13.7 Usage Notes 13.7.1 Internal Clock Switching and TCG Operation Depending on the timing, TCG may be incremented by a switch between different internal clock sources. Table 13.3 shows the relation between internal clock switchover timing (by write to bits CKS1 and CKS0) and TCG operation. When TCG is internally clocked, an increment pulse is generated on detection of the falling edge of an internal clock signal, which is divided from the system clock (φ) or subclock (φW).
Section 13 Timer G No. Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation 3 Goes from high level to low level Clock before switching Clock after switching * Count clock TCG N N+1 N+2 Write to CKS1 and CKS0 4 Goes from high level to high level Clock before switching Clock after switching Count clock TCG N N+1 N+2 Write to CKS1 and CKS0 Note: 13.7.2 * The switchover is seen as a falling edge, and TCG is incremented.
Section 13 Timer G Table 13.
Section 13 Timer G When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 13.8 shows the procedure for handling of the port mode register and clearing of the interrupt request flag.
Section 13 Timer G 13.8 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1. Figure 13.9 shows an example of the operation in this case. Input capture input signal H'FF Input capture register GF Input capture register GR H'00 TCG Counter cleared Figure 13.9 Timer G Application Example Rev. 2.00 Jul.
Section 14 16-Bit Timer Pulse Unit (TPU) Section 14 16-Bit Timer Pulse Unit (TPU) Microcontrollers of the H8/38099 Group have an on-chip 16-bit timer pulse unit (TPU) that comprises two 16-bit timer channels. The function list of the TPU is shown in table 14.1. A block diagram of the TPU is shown in figure 14.1. 14.
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.
Section 14 16-Bit Timer Pulse Unit (TPU) TGRB TGRB TCNT TCNT TGRA TSR Module data bus TIER TIER TSR TIOR TIOR TGRA Bus interface Internal data bus TSTR Control logic TMDR Channel 2 TCR TMDR Common [Legend] TSTR: Timer start register TSYR: Timer synchro register TCR: Timer control register TMDR: Timer mode register TCNT: Timer counter Channel 1 Channel 2: TIOCA1 TIOCB1 TIOCA2 TIOCB2 TCR Input/output pins Channel 1: Control logic for channels 1 and 2 External clock: φ/4 φ/16 φ/64 φ/256
Section 14 16-Bit Timer Pulse Unit (TPU) 14.3 Register Descriptions The TPU has the following registers for each channel.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.3.1 Timer Control Register (TCR) TCR controls TCNT operation for each channel. The TPU has a total of two TCR registers, one for each channel. TCR should be set when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 0 Reserved 6 CCLR1 0 R/W Counter Clear 1 and 0 5 CCLR0 0 R/W These bits select the TCNT counter clearing source. See table 14.3 for details.
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.3 CCLR1 and CCLR0 (Channels 1 and 2) Channel Bit 6 CCLR1 Bit 5 CCLR0 Description 1, 2 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* 1 Note: * Synchronous operation is selected by setting the SYNC bit in TSYR to 1. Table 14.
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.5 TPSC2 to TPSC0 (Channel 2) Bit 2 Channel TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on φ/1024 0 1 1 0 1 14.3.
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.6 MD1 to MD0 Bit 1 MD1 Bit 0 MD0 Description 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 1 14.3.3 Timer I/O Control Register (TIOR) TIOR controls TGR. The TPU has a total of two TIOR registers, one for each channel. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0).
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has a total of two TIER registers, one for each channel. Bit Bit Name Initial Value R/W Description 7 0 R/W Reserved 6 1 This bit is readable/writable. Reserved This bit is always read as 1 and cannot be modified. 5 0 Reserved The write value should always be 0.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.3.5 Timer Status Register (TSR) TSR indicates the status for each channel. The TPU has a total of two TSR registers, one for each channel. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved 5 0 These bits are always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. 4 TCFV 0 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred.
Section 14 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W 0 TGFA 0 R/(W)* Input Capture/Output Compare Flag A Description Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] • TCNT = TGRA and TGRA is functioning as output compare register • The TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Clearing condition] • Note: 14.3.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.3.8 Timer Start Register (TSTR) TSTR selects TCNT operation/stoppage for channels 1 and 2. TCNT starts counting for channel in which the corresponding bit is set to 1. When setting the operating mode in TMDR or setting the TCNT count clock in TCR, first stop the TCNT operation. Bit Bit Name Initial Value R/W Description 7 to 3 All 0 R/W Reserved The write value should always be 0.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation of TCNT for each channel. Synchronous operation is performed for channel in which the corresponding bit in TSYR is set to 1. Bit Bit Name Initial Value R/W Description 7 to 3 All 0 R/W Reserved The write value should always be 0.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.4 Interface to CPU 14.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the CPU is 16 bits wide, these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 14.2. Internal data bus H CPU L Module data bus Bus interface Upper 8 bits Lower 8 bits TCNT Figure 14.2 16-Bit Register Access Operation [CPU ↔ TCNT (16 Bits)] 14.4.
Section 14 16-Bit Timer Pulse Unit (TPU) CPU Internal data bus H L Module data bus Bus interface TMDR Figure 14.4 8-Bit Register Access Operation [CPU ↔ TMDR (Lower 8 Bits)] Rev. 2.00 Jul.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.5 Operation 14.5.1 Basic Functions Each channel has TCNT and TGR. TCNT performs up-counting, and is also capable of freerunning operation, periodic counting, and external event counting. TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST1 and CST2 is set to 1 in TSTR, TCNT for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example.
Section 14 16-Bit Timer Pulse Unit (TPU) (b) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
Section 14 16-Bit Timer Pulse Unit (TPU) Figure 14.7 illustrates periodic counter operation. TCNT value Counter cleared by TGR compare match TGR H'0000 Time CST bit Flag cleared by software TGF Figure 14.7 Periodic Counter Operation (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match Figure 14.
Section 14 16-Bit Timer Pulse Unit (TPU) (b) Examples of Waveform Output Operation Figure 14.9 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
Section 14 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. (a) Example of Input Capture Operation Setting Procedure Figure 14.11 shows an example of the setting procedure for input capture operation.
Section 14 16-Bit Timer Pulse Unit (TPU) (b) Example of Input Capture Operation Figure 14.12 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the input capture input edge of the TIOCA pin, the falling edge has been selected as the input capture input edge of the TIOCB pin, and counter clearing by TGRB input capture has been designated for TCNT.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.5.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Synchronous operation can be set for each channel.
Section 14 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 14.14 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 1 and 2, TGRB_1 compare match has been set as the channel 1 counter clearing source, and synchronous clearing has been set for the channel 2 counter clearing source. Two-phase PWM waveforms are output from pins TIOC1A and TIOC2A.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.5.3 Operation with Cascaded Connection Operation as a 32-bit counter can be performed by cascading two 16-bit counter channels. This function is enabled when the TPSC2 to TPSC0 bits in TCR are set to count on TCNT2 overflow for the channel 1 counter clock. Table 14.11 shows the counter combination used in operation with the cascaded connection. Table 14.
Section 14 16-Bit Timer Pulse Unit (TPU) (2) Example of Operation with Cascaded Connection Figure 14.16 shows an example of operation with cascaded connection, where TCNT1 is set to count TCNT2 overflow, TCRA_1 and TCRA_2 are set to be input capture registers, and the TIOC pin rising edge is selected. If rising edges are input simultaneously to the TIOCA1 and TIOCA2 pins, the upper 16 bits of 32bit data are transferred to TGRA_1 and the lower 16 bits are transferred to TGRA_2.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below.
Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.12 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 1 TGRA_1 TIOCA1 PWM Mode 2* TIOCA1 TGRB_1 2 TIOCB1 TGRA_2 TIOCA2 TIOCA2 TGRB_2 Note: (3) * TIOCB2 In PWM mode 2, PWM output is not possible for TGR in which the period is set. Example of PWM Mode Setting Procedure Figure 14.17 shows an example of the PWM mode setting procedure.
Section 14 16-Bit Timer Pulse Unit (TPU) (4) Examples of PWM Mode Operation Figure 14.18 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB are used as the duty levels. TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 14.
Section 14 16-Bit Timer Pulse Unit (TPU) Figure 14.19 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 1 and 2, TGRB_2 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_1, TGRB_1, and TGRA_2), outputting a 3-phase PWM waveform.
Section 14 16-Bit Timer Pulse Unit (TPU) (1) When the value of the duty register is larger than that of the cycle register TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten Time H'0000 0% duty TIOCA (2) When the values of the duty and cycle registers are identical Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA (3) When the value of th
Section 14 16-Bit Timer Pulse Unit (TPU) 14.6 Interrupt Sources There are two kinds of TPU interrupt source; TGR input capture/compare match and TCNT overflow. Each interrupt source has its own status flag and enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt source is generated, the corresponding status flag in TSR is set to 1.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.7 Operation Timing 14.7.1 Input/Output Timing (1) TCNT Count Timing Figure 14.21 shows TCNT count timing in internal clock operation, and figure 14.22 shows TCNT count timing in external clock operation. φ Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 14.21 Count Timing in Internal Clock Operation φ External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 Figure 14.
Section 14 16-Bit Timer Pulse Unit (TPU) (2) Output Compare Output Timing A compare match signal is generated in the last state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 14.
Section 14 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Signal Timing Figure 14.24 shows input capture signal timing. φ Input capture input Input capture signal TCNT N N+1 N+2 N TGR N+2 Figure 14.24 Input Capture Input Signal Timing (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 14.25 shows the timing when counter clearing on compare match is specified, and figure 14.26 shows the timing when counter clearing on input capture is specified.
Section 14 16-Bit Timer Pulse Unit (TPU) φ Input capture signal Counter clear signal H'0000 N TCNT N TGR Figure 14.26 Counter Clear Timing (Input Capture) 14.7.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 14.27 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 14.
Section 14 16-Bit Timer Pulse Unit (TPU) (2) TGF Flag Setting Timing in Case of Input Capture Figure 14.28 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. φ Input capture signal N TCNT TGR N TGF flag TGI interrupt Figure 14.28 TGI Interrupt Timing (Input Capture) (3) TCFV Flag Setting Timing Figure 14.29 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing.
Section 14 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 14.30 shows the timing for status flag clearing by the CPU. TSR write cycle T2 T1 φ TSR address Address Write signal Status flag Interrupt request signal Figure 14.30 Timing for Status Flag Clearing by CPU 14.8 Usage Notes 14.8.1 Module Standby Function Setting TPU operation can be disabled or enabled using the clock stop register.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.8.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the last state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: φ f= (N + 1) Where 14.8.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.8.5 Contention between TCNT Write and Increment Operation If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes priority and TCNT is not incremented. Figure 14.32 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 14.32 Contention between TCNT Write and Increment Operation Rev. 2.00 Jul.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.8.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes priority and the compare match signal is inhibited. A compare match does not occur even if the previous value is written. Figure 14.33 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Compare match signal Inhibited TCNT N N+1 TGR N M TGR write data Figure 14.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.8.7 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, data that is read will be data after input capture transfer. Figure 14.34 shows the timing in this case. TGR read cycle T2 T1 φ TGR address Address Read signal Input capture signal TGR Internal data bus X M M Figure 14.34 Contention between TGR Read and Input Capture Rev. 2.00 Jul.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.8.8 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes priority and the write to TGR is not performed. Figure 14.35 shows the timing in this case. TGR write cycle T2 T1 φ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 14.35 Contention between TGR Write and Input Capture Rev. 2.00 Jul.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.8.9 Contention between Overflow and Counter Clearing If overflow and counter clearing occur simultaneously, the TCFV flag in TSR is not set and TCNT clearing takes priority. Figure 14.36 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF TCFV Disabled Figure 14.36 Contention between Overflow and Counter Clearing Rev. 2.
Section 14 16-Bit Timer Pulse Unit (TPU) 14.8.10 Contention between TCNT Write and Overflow If there is an up-count in the T2 state of a TCNT write cycle and overflow occurs, the TCNT write takes priority and the TCFV flag in TSR is not set. Figure 14.37 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT TCNT write data H'FFFF M TCFV flag Figure 14.37 Contention between TCNT Write and Overflow 14.8.
Section 15 Asynchronous Event Counter (AEC) Section 15 Asynchronous Event Counter (AEC) The asynchronous event counter (AEC) is an event counter that is incremented by external event clock or internal clock input. Figure 15.1 shows a block diagram of the asynchronous event counter. 15.1 Features • Can count asynchronous events Can count external events input asynchronously without regard to the operation of system clocks (φ) or subclocks (φSUB).
Section 15 Asynchronous Event Counter (AEC) IRREC φ ECCR PSS ECCSR OVH AEVH AEVL Edge sensing circuit OVL ECH (8 bits) CK ECL (8 bits) CK Edge sensing circuit IRQAEC Edge sensing circuit IECPWM To CPU interrupt (IRREC2) ECPWCR PWM waveform generator φ/2, φ/4, φ/8, φ/16, φ/32, φ/64 ECPWDR AEGSR [Legend] ECPWCR: ECPWDR: AEGSR: ECCSR: Event counter PWM compare register Event counter PWM data register Input pin edge select register Event counter control/status register ECL: ECCR: ECH: PSS:
Section 15 Asynchronous Event Counter (AEC) 15.3 Register Descriptions The asynchronous event counter has the following registers. • Event counter PWM compare register (ECPWCR) • Event counter PWM data register (ECPWDR) • Input pin edge select register (AEGSR) • Event counter control register (ECCR) • Event counter control/status register (ECCSR) • Event counter H (ECH) • Event counter L (ECL) 15.3.
Section 15 Asynchronous Event Counter (AEC) 15.3.2 Event Counter PWM Data Register (ECPWDR) ECPWDR controls data of the event counter PWM waveform generator. ECPWDR should be read from or written to in word units.
Section 15 Asynchronous Event Counter (AEC) 15.3.3 Input Pin Edge Select Register (AEGSR) AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins. Bit Bit Name Initial Value R/W Description 7 AHEGS1 0 R/W AEC Edge Select H 6 AHEGS0 0 R/W Select rising, falling, or both edge sensing for the AEVH pin.
Section 15 Asynchronous Event Counter (AEC) 15.3.4 Event Counter Control Register (ECCR) ECCR controls the counter input clock and IRQAEC/IECPWM. Bit Bit Name Initial Value R/W Description 7 ACKH1 0 R/W AEC Clock Select H 6 ACKH0 0 R/W Select the clock used by ECH. 00: AEVH pin input 01: φ/2 10: φ/4 11: φ/8 5 ACKL1 0 R/W AEC Clock Select L 4 ACKL0 0 R/W Select the clock used by ECL.
Section 15 Asynchronous Event Counter (AEC) 15.3.5 Event Counter Control/Status Register (ECCSR) ECCSR controls counter overflow detection, counter resetting, and count-up function. Bit Bit Name Initial Value R/W Description 7 OVH 0 R/(W)* Counter Overflow H This is a status flag indicating that ECH has overflowed.
Section 15 Asynchronous Event Counter (AEC) Bit Bit Name Initial Value R/W Description 2 CUEL 0 R/W Count-Up Enable L Enables event clock input to ECL. 0: ECL event clock input is disabled (ECL value is retained) 1: ECL event clock input is enabled 1 CRCH 0 R/W Counter Reset Control H Controls resetting of ECH. 0: ECH is reset 1: ECH reset is cleared and count-up function is enabled 0 CRCL 0 R/W Counter Reset Control L Controls resetting of ECL.
Section 15 Asynchronous Event Counter (AEC) 15.3.6 Event Counter H (ECH) ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. When word access is performed for ECH, the upper 8 bits and lower 8 bits of a 16-bit event counter can be read from in one bus cycle.
Section 15 Asynchronous Event Counter (AEC) 15.4 Operation 15.4.1 16-Bit Counter Operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0. Note that the input clock is enabled when IRQAEC is high or IECPWM is high.
Section 15 Asynchronous Event Counter (AEC) 15.4.2 8-Bit Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Section 15 Asynchronous Event Counter (AEC) 15.4.3 IRQAEC Operation When the ECPWME bit in AEGSR is 0, the ECH and ECL input clocks are enabled when IRQAEC goes high. When IRQAEC goes low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually. IRQAEC can also operate as an interrupt source.
Section 15 Asynchronous Event Counter (AEC) Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this condition, the output of the event counter PWM is fixed low. Table 15.2 Examples of Event Counter PWM Operation Conditions: fosc = 4 MHz, fφ = 4 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11, ECPWDR value (Ndr) = H'16E3 Clock Source Selection Clock Source Cycle (T)* toff = T × ECPWDR ECPWCR Value (Ncm) Value (Ndr) (Ndr + 1) φ/2 0.
Section 15 Asynchronous Event Counter (AEC) 15.5 Operating States of Asynchronous Event Counter The operating states of the asynchronous event counter are shown in table 15.3. Table 15.
Section 15 Asynchronous Event Counter (AEC) 15.6 Usage Notes 1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in 8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the counter. The correct value will not be returned if the event counter increments while being read. 2. For input to the AEVH and AEVL pins, use a clock with a frequency of up to 4.2 MHz within the range from 1.8 to 3.6 V and up to 10 MHz within the range from 2.
Section 15 Asynchronous Event Counter (AEC) 6. As synchronization is established internally when an IRQAEC interrupt is generated, a maximum error of 1 tcyc will occur between clock halting and interrupt acceptance. Rev. 2.00 Jul.
Section 16 Watchdog Timer Section 16 Watchdog Timer This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog timer function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 16.
Section 16 Watchdog Timer Figure 16.1 shows a block diagram of the WDT. On-chip WDT oscillator φ TCSRWD1 PSS TCWD Internal data bus TMWD TCSRWD2 [φw/16 or φw/256] Interrupt/reset control [Legend] TCSRWD1: TCSRWD2: TCWD: TMWD: PSS: Timer control/status register WD1 Timer control/status register WD2 Timer counter WD Timer mode register WD Prescaler S Figure 16.1 Block Diagram of Watchdog Timer 16.2 Register Descriptions The watchdog timer has the following registers.
Section 16 Watchdog Timer 16.2.1 Timer Control/Status Register WD1 (TCSRWD1) TCSRWD1 performs the TCSRWD1 and TCWD write control. TCSRWD1 also controls the watchdog timer operation and indicates the operating state. TCSRWD1 must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. Bit Bit Name Initial Value R/W Description 7 B6WI 1 R/W Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0.
Section 16 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 1 R/W Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0.
Section 16 Watchdog Timer 16.2.2 Timer Control/Status Register WD2 (TCSRWD2) TCSRWD2 performs the TCSRWD2 write control, mode switching, and interrupt control. TCSRWD2 must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. Bit 7 Bit Name OVF Initial Value 0 R/W Description 1 R/(W)* Overflow Flag Indicates that TCWD has overflowed (changes from H'FF to H'00).
Section 16 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 to 0 All 1 Reserved These bits are always read as 1. Notes: 1. Only 0 can be written to clear the flag. 2. Write operation is necessary because this bit controls data writing to other bit. This bit is always read as 1. 3. Writing is possible only when the write conditions are satisfied. 16.2.3 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter.
Section 16 Watchdog Timer 16.2.4 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1. 3 CKS3 0 R/W Clock Select 3 to 0 2 CKS2 0 R/W Select the clock to be input to TCWD.
Section 16 Watchdog Timer 16.3 Operation 16.3.1 Watchdog Timer Mode The watchdog timer is provided with an 8-bit up-counter. To use it as the watchdog timer, clear the WT/IT bit in TCSRWD2 to 0. (To write the WT/IT bit, two write accesses are required.) If 1 is written to the WDON bit and 0 to the B2WI bit simultaneously when the TCSRWE bit in TCSRWD1 is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD1 are required.
Section 16 Watchdog Timer 16.3.2 Interval Timer Mode Figure 16.3 shows the operation in interval timer mode. To use the WDT as an interval timer, set the WT/IT bit in TCSRWD2 to 1. When the WDT is used as an interval timer, an interval timer interrupt request is generated each time the TCWD overflows. Therefore, an interval timer interrupt can be generated at intervals.
Section 16 Watchdog Timer 16.4 Interrupt During interval timer mode operation, an overflow generates an interval timer interrupt. The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSRWD2. The OVF flag must be cleared to 0 in the interrupt handling routine. 16.5 Usage Notes 16.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode If modes are switched between watchdog timer and interval timer, while the WDT is operating, an error may occur in the count value.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Section 17 Serial Communications Interface 3 (SCI3, IrDA) The serial communications interface 3 (SCI3) can handle both asynchronous and clock synchronous serial communications. The asynchronous method allows the handling of serial data communications with standard asynchronous communications chips such as Universal Asynchronous Receiver/Transmitters (UARTs) and Asynchronous Communications Interface Adapters (ACIAs).
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Clock synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors detected Note: When using this function, do not use the on-chip oscillator for the system clock. Rev. 2.00 Jul.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Figures 17.1 (1), 17.1 (2), and 17.1 (3) show block diagrams of the SCI3_1, SCI3_2, and SCI3_3, respectively.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) SCK32 Internal clock (φ/64, φ/16, φw/2, φ) External clock Baud rate generator BRC3_2 BRR3_2 SMR3_2 Transmit/receive control circuit SCR3_2 SSR3_2 TXD32 RXD32 TSR3_2 TDR3_2 RSR3_2 RDR3_2 Internal data bus Clock SPCR Interrupt request (TEI32, TXI32, RXI32, ERI32) [Legend] RSR3_2: RDR3_2: TSR3_2: TDR3_2: SMR3_2: SCR3_2: SSR3_2: BRR3_2: BRC3_2: SPCR: Receive shift register 3_2 Receive data register 3_2 Transmit shift register 3_2 Transm
Section 17 Serial Communications Interface 3 (SCI3, IrDA) SCK33 Internal clock (φ/64, φ/16, φw/2, φ) External clock Baud rate generator BRC3_3 BRR3_3 SMR3_3 Transmit/receive control circuit SCR3_3 SSR3_3 TXD33 RXD33 TSR3_3 TDR3_3 RSR3_3 RDR3_3 Internal data bus Clock SPCR2 Interrupt request (TEI33, TXI33, RXI33, ERI33) [Legend] RSR3_3: RDR3_3: TSR3_3: TDR3_3: SMR3_3: SCR3_3: SSR3_3: BRR3_3: BRC3_3: SPCR2: Receive shift register 3_3 Receive data register 3_3 Transmit shift register 3_3 Tran
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.2 Input/Output Pins Table 17.2 shows the SCI3 pin configuration. Table 17.2 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK31, SCK32, SCK33 I/O SCI3 clock input/output SCI3 receive data input RXD31, RXD32, RXD33 Input SCI3 receive data input SCI3 transmit data output TXD31, TXD32, TXD33 Output SCI3 transmit data output 17.3 Register Descriptions The SCI3 has the following registers for each channel.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.3.1 Receive Shift Register (RSR) RSR is a shift register that receives serial data input from the RXD3 pin and converts it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 17.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.3.5 Serial Mode Register (SMR) SMR sets the SCI3's serial communication format and selects the clock source for the on-chip baud rate generator. SMR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Bit Bit Name Initial Value R/W Description 4 PM 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number, in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φW/2 clock (n = 0) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) When φW/2 clock is selected in subactive mode and subsleep mode, the SCI3 is only enabled when φW/2 clock is selected for the CPU operating clock.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.3.6 Serial Control Register (SCR) SCR enables or disables SCI3 transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, refer to section 17.8, Interrupt Requests. SCR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.3.7 Serial Status Register (SSR) SSR consists of status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. SSR is initialized to H'84 by a reset or in standby mode, watch mode, or module standby mode. Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* Transmit Data Register Empty Description Indicates that transmit data is stored in TDR.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Bit Bit Name Initial Value R/W 5 OER 0 R/(W)* Overrun Error Description [Setting condition] • An overrun error occurs in reception [Clearing condition] • Writing of 0 to bit OER after reading OER = 1 When bit RE in SCR is cleared to 0, bit OER is not affected and retains its previous state. When an overrun error occurs, RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Bit Bit Name Initial Value R/W 3 PER 0 R/(W)* Parity Error Description [Setting condition] • A parity error is generated during reception [Clearing condition] • Writing of 0 to bit PER after reading PER = 1 When bit RE in SCR is cleared to 0, bit PER is not affected and retains its previous state. Receive data in which a parity error has occurred is still transferred to RDR, but bit RDRF is not set.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.3.8 Bit Rate Register (BRR) BRR is an 8-bit readable/writable register that specifies the bit rate. BRR is initialized to H'FF. Tables 17.3 and 17.4 show examples of the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in asynchronous mode. Table 17.6 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in these tables are values in active (high-speed) mode.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (1) 32.8 kHz 38.4 kHz 2 MHz 2.097152 MHz Bit Rate (bit/s) n N Error (%) n N 110 — — — — — — 2 35 –1.36 150 — — — 0 3 0.00 2 25 0.16 200 — — — 0 2 0.00 2 19 –2.34 250 0 1 2.50 — — — 0 249 300 — — — 0 1 0.00 0 600 — — — 0 0 0.00 1200 — — — — — 2400 — — — — — N Error (%) 2 36 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (2) 2.4576 MHz 3 MHz 3.6864 MHz 4 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 43 –0.83 2 52 0.50 2 64 0.70 2 70 0.03 150 2 31 0.00 2 38 0.16 2 47 0.00 2 51 0.16 200 2 23 0.00 2 28 1.02 2 35 0.00 2 38 0.16 250 2 18 1.05 2 22 1.90 2 28 –0.69 2 30 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (3) 4.194304 MHz 4.9152MHz 5 MHz Bit Rate (bit/s) n N Error (%) 110 2 73 0.64 2 86 0.31 2 150 2 54 –0.70 2 63 0.00 2 200 2 40 –0.10 2 47 0.00 2 250 2 32 –0.70 2 37 1.05 300 2 26 1.14 2 31 600 0 217 0.21 0 1200 0 108 0.21 2400 0 54 –0.70 4800 0 26 1.14 0 31 0.00 0 9600 0 13 –2.48 0 15 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (4) Bit Rate (bit/s) n 6.144 MHz 7.3728 MHz 8 MHz 9.8304 MHz 10 MHz N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 108 0.08 2 130 –0.07 2 141 0.03 2 174 –0.26 2 177 –0.25 150 2 79 0.00 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 200 2 59 0.00 2 71 0.00 2 77 0.16 2 95 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (1) 32.8 kHz 38.4 kHz 2 MHz Bit Rate (bit/s) n 110 — — — 0 10 –0.83 2 150 0 6 –2.38 0 7 0.00 2 200 0 4 2.50 0 5 0.00 2 250 0 3 2.50 — — — 300 — — — 0 3 600 — — — 0 1200 — — — 2400 — — 4800 — 9600 — 19200 2.097152 MHz Error (%) n N Error (%) 70 0.03 2 73 0.64 51 0.16 2 54 –0.70 38 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (2) 2.4576 MHz 3 MHz 3.6864 MHz 4 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 86 0.31 2 106 –0.44 2 130 –0. 07 2 141 0.03 150 2 63 0.00 2 77 0.16 2 95 0.00 2 103 0.16 200 2 47 0.00 2 58 –0.69 2 71 0.00 2 77 0.16 250 2 37 1.05 2 46 –0.27 2 57 –0.69 2 62 –0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (3) 4.194304 MHz 4.9152MHz 5 MHz 6 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 148 –0.04 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 108 0.21 2 127 0.00 2 129 0.16 2 155 0.16 200 2 81 –0.10 2 95 0.00 2 97 –0.35 2 116 0.16 250 2 65 –0.70 2 76 –0.26 2 77 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (4) Bit Rate (bit/s) n 6.144 MHz 7.3728 MHz 8 MHz N Error (%) n N Error (%) n N 9.8304 MHz Error (%) n Error (%) N 10 MHz n N Error (%) 110 2 217 0.08 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 159 0.00 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 200 2 119 0.00 2 143 0.00 2 155 0.16 2 191 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.6 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Rate (bit/s) φ (MHz) ABCS = 0 ABCS = 1* 0.0328* 1 512 0.0384* 1 600 2 2 Setting n N 1025 0 0 1200 0 0 62500 125000 0 0 2.097152 65536 131072 0 0 2.4576 76800 153600 0 0 3 93750 187500 0 0 3.6864 115200 230400 0 0 4 125000 250000 0 0 4.194304 131072 262144 0 0 4.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.7 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1) φ 32.8 kHz 38.4 kHz 2 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 200 0 20 –2.38 0 23 0.00 2 155 0.16 250 0 15 2.50 0 18 1.05 2 124 0.00 300 0 13 –2.38 0 15 0.00 2 103 0.16 500 0 7 2.50 2 62 –0.79 1k 0 3 2.50 2 30 0.81 2.5 k 0 199 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.7 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2) φ 4 MHz 8 MHz Bit Rate (bit/s) n N Error (%) n N 200 3 77 0.16 3 250 2 249 0.00 300 2 500 n N Error (%) 155 0.16 3 194 0.16 3 124 0.00 3 155 0.16 207 0.16 3 103 0.16 3 129 0.16 2 124 0.00 2 249 0.00 3 77 0.16 1k 2 62 –0.79 2 124 0.00 2 155 0.16 2.5 k 2 24 0.00 2 49 0.00 2 62 –0.79 5k 0 199 0.00 2 24 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.8 Correspondence between n and Clock SMR Setting n Clock CKS1 CKS0 0 φ 0 0 0 φW/2* 0 1 2 φ/16 1 0 3 φ/64 1 1 Note: In subactive or subsleep mode, the SCI3_1, SCI3_2, and SCI3_3 interfaces can operate only when the CPU clock is φW/2. 17.3.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Bit Bit Name Initial Value R/W Description 3 SCINV3 0 R/W TXD32 Pin Output Data Inversion Switch Selects whether the logic level of output data of the TXD32 pin is inverted or not. 0: TXD32 output data is not inverted. 1: TXD32 output data is inverted. 2 SCINV2 0 R/W RXD32 Pin Input Data Inversion Switch Selects whether the logic level of input data of the RXD32 pin is inverted or not. 0: RXD32 input data is not inverted.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.3.10 Serial Port Control Register 2 (SPCR2) SPCR2 selects the function of the TXD33 pin and selects whether or not data input on the RXD33 pin and output via the TXD33 pin are inverted. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1 and cannot be modified. 4 SPC33 0 R/W PE2/TXD33 Pin Function Switch Selects whether pin PE2/TXD33 is used as PE2 or as TXD33.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.3.11 IrDA Control Register (IrCR) IrCR controls the IrDA operation of the SCI3_1. Bit Bit Name Initial Value R/W 7 IrE 0 R/W Description IrDA Enable Selects whether the SCI3_1 I/O pins function as the SCI or IrDA.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.3.12 Serial Extended Mode Register (SEMR) SEMR controls extended functions of the SCI3_1, i.e. specifies the basic clock in asynchronous mode. Bit Bit Name Initial Value R/W Description 7 to 4 All 0 Reserved 3 ABCS 0 R/W The write value should always be 0. Asynchronous Mode Basic Clock Select Selects the basic clock for one-bit interval in asynchronous mode.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.4 Operation in Asynchronous Mode Figure 17.2 shows the general format for asynchronous serial communication. Each frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In reception in asynchronous mode, synchronization is with falling edges of the start bits.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.4.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3's serial clock source, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock signal is input on the SCK3 pin, its frequency should be 16 times the bit rate (or 8 times the bit rate when the ABCS bit in SEMR is set to 1*).
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.4.2 SCI3 Initialization Follow the flowchart as shown in figure 17.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.4.3 Data Transmission Figure 17.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Start transmission Set SPC3 bit in SPCR or SPCR2 to 1 [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR Yes [2] Continue data transmission? No Read TEND flag in SSR [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. (After the TE bit is set to 1, one frame of 1 is output, then transmission is possible.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.4.4 Serial Data Reception Figure 17.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Start bit Serial data 1 0 Receive data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 Receive data D0 D1 1 frame Parity Stop bit bit D7 0/1 Mark state (idle state) 0 1 1 frame RDRF FER LSI operation RXI3 interrupt request generated User processing 0 stop bit detected RDRF cleared to 0 RDR data read ERI3 request in response to framing error Framing error processing Figure 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 End Figure 17.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) Rev. 2.00 Jul.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.5 Operation in Clock Synchronous Mode Figure 17.9 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.5.3 Serial Data Transmission Figure 17.10 shows an example of SCI3 operation for transmission in clock synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Figure 17.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.5.4 Serial Data Reception (Clock Synchronous Mode) Figure 17.12 shows an example of SCI3 operation for reception in clock synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. The SCI3 stores the received data in RSR. 3.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.13 shows a sample flowchart for serial data reception. Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1? [4] No [3] Overrun error processing (Continued below) Read RDRF flag in SSR [2] [4] No RDRF = 1? Yes Read the OER flag in SSR to determine if there is an error.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.5.5 Simultaneous Serial Data Transmission and Reception Figure 17.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) [Legend] MPB: Multiprocessor bit (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Figure 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.6.1 Multiprocessor Serial Data Transmission Figure 17.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.6.2 Multiprocessor Serial Data Reception Figure 17.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI3 interrupt request is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame 1 frame MPIE RDRF RDR value ID1 LSI operation RXI3 interrupt request generated MPIE cleared to 0 User processing RDRF flag cleared to 0 RXI3 interrupt request is not generated, and RDR retains its state RDR data read When data is not this station's ID, MPIE is
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.7 IrDA Operation IrDA operation can be used with the SCI3_1. Figure 17.19 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in IrCR, the TXD31 and RXD31 pins in the SCI3_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTXD and IrRXD pins).
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.7.1 Transmission During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 17.20). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in IrCR. According to the standard, the high-level pulse width is defined to be 1.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.7.2 Reception During reception, IR frames are converted to UART frames using the IrDA interface before inputting to the SCI3_1. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 µs, the minimum width allowed, the pulse is not recognized. 17.7.3 High-Level Pulse Width Selection Table 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.8 Interrupt Requests The SCI3 creates the following six interrupt requests: transmit end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 17.14 shows the interrupt sources. Table 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) These interrupts are shown in table 17.15. Table 17.15 Transmit/Receive Interrupts Interrupt Flags Interrupt Request Conditions Notes RXI3 RDRF When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, an RXI3 is enabled and an interrupt is requested. (See figure 17.21 (a).
Section 17 Serial Communications Interface 3 (SCI3, IrDA) RDR RDR RSR (reception in progress) RSR↑ (reception completed, transfer) RXD3 pin RDRF RDRF = 0 → RXD3 pin 1 (RXI3 request when RIE = 1) Figure 17.21 (a) RDRF Setting and RXI3 Interrupt TDR (next transmit data) TDR TSR (transmission in progress) ↓ TSR (transmission completed, transfer) TXD3 pin TXD3 pin TDRE → TDRE = 0 1 (TXI3 request when TIE = 1) Figure 17.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.9 Usage Notes 17.9.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD3 pin value directly. In a break, the input from the RXD3 pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 17.9.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.9.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate (8 times the transfer rate when the ABCS bit in SEMR is set to 1). In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.9.5 Note on Switching SCK3 Pin Function If pin SCK3 is used as a clock output pin by the SCI3 in clock synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock (φ) cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.9.7 Relation between RDR Reading and bit RDRF In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) 17.9.8 Transmit and Receive Operations when Making State Transition Make sure that transmit and receive operations have completely finished before carrying out state transition processing. 17.9.9 Setting in Subactive or Subsleep Mode In subactive or subsleep mode, the SCI3 interface can operate only when the CPU clock is φW/2. The SA1 and SA0 bits in SYSCR2 should be set to 1 and 0, respectively. 17.9.
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Rev. 2.00 Jul.
Section 18 Serial Communication Interface 4 (SCI4) Section 18 Serial Communication Interface 4 (SCI4) The serial communication interface 4 (SCI4) can handle clock synchronous serial communication with the 8-bit buffer. The SCI4 is supported only by the F-ZTAT version. When the on-chip emulator debugger etc. is used, the SCK4, SI4, and SO4 pins of the SCI4 are used by the system, and the SCI4 is not available for the user. 18.
Section 18 Serial Communication Interface 4 (SCI4) Figure 18.1 shows a block diagram of the SCI4. φ PSS SCSR4 SCK4 SCR4 TDR4 SR4 SI4 SO4 Internal data bus Transmit/receive control circuit RDR4 TEI TXI RXI ERI [Legend] SCSR4: Serial control status register 4 SCR4: Serial control register 4 TDR4: Transmit data register 4 SR4: Shift register 4 RDR4: Receive data register 4 Figure 18.1 Block Diagram of SCI4 18.2 Input/Output Pins Table 18.1 shows the SCI4 pin configuration. Table 18.
Section 18 Serial Communication Interface 4 (SCI4) 18.3 Register Descriptions The SCI4 has the following registers. • Serial control register 4 (SCR4) • Serial control/status register 4 (SCSR4) • Transmit data register 4 (TDR4) • Receive data register 4 (RDR4) • Shift Register 4 (SR4) 18.3.1 Serial Control Register 4 (SCR4) SCR4 enables or disables interrupt requests and controls SCI4 transfer operations.
Section 18 Serial Communication Interface 4 (SCI4) Bit Bit Name Initial Value R/W Description 5 TEIE 0 R/W Transmit End Interrupt Enable Enables or disables a transmit end interrupt (TEI) request when there is no valid transmit data in TDR4 during transmission of MSB data. TEI can be cleared by clearing the TEND flag in SCSR4 to 0 after the flag is read as 1 or clearing this bit to 0.
Section 18 Serial Communication Interface 4 (SCI4) Bit Bit Name Initial Value R/W Description 2 SRES 0 R/W Forcible Reset When the internal sequencer is forcibly initialized, 1 should be written to this bit. When 1 is written to this flag, the internal sequencer is forcibly reset and then this flag is automatically cleared to 0. Note that the values of the internal registers are retained. (The TDRE flag in SCSR4 is set to 1 and the RDRF, ORER, and TEND flags are cleared to 0.
Section 18 Serial Communication Interface 4 (SCI4) 18.3.2 Serial Control/Status Register 4 (SCSR4) SCSR4 indicates the operating state and error state, selects the clock source, and controls the prescaler division ratio. SCSR4 can be read from or written to by the CPU at any time. 1 cannot be written to flags TDRE, RDRF, ORER, and TEND. To clear these flags to 0, 1 should be read from them in advance.
Section 18 Serial Communication Interface 4 (SCI4) Bit Bit Name Initial Value R/W 5 ORER 0 R/(W)* Overrun Error Description Indicates that an overrun error occurs during reception and then abnormal termination occurs. In transfer mode, the output level of the SO4 pin is fixed to low while this flag is set to 1. When the RE bit in SCR4 is cleared to 0, the ORER flag is not affected and retains its previous state.
Section 18 Serial Communication Interface 4 (SCI4) Table 18.2 shows a prescaler division ratio and transfer clock cycle. Table 18.2 Prescaler Division Ratio and Transfer Clock Cycle (Internal Clock) Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 0 0 0 Transfer Clock Cycle Function CKS0 Prescaler Division Ratio φ= 5 MHz φ= 2.5 MHz Clock Source Pin Function 0 0 φ/1024 204.8 µs 409.6 µs Internal clock SCK4 output pin 0 0 1 φ/256 51.2 µs 102.
Section 18 Serial Communication Interface 4 (SCI4) 18.3.3 Transmit Data Register 4 (TDR4) TDR4 is an 8-bit register that stores data for serial transmission. When the SCI4 detects that SR4 is empty, it transfers the transmit data written in TDR4 to SR4 and starts serial transmission. If the next transmit data is written to TDR4 while serial data in SR4 is being transmitted, continuous serial transmission is possible. TDR4 can be read from or written to by the CPU at any time. TDR4 is initialized to H'FF.
Section 18 Serial Communication Interface 4 (SCI4) 18.4 Operation The SCI4 is a serial communication interface that transmits and receives data in synchronization with a clock pulse and is suitable for high-speed serial communications. The data transfer format is fixed to 8-bit data. The internal clock or external clock can be selected as a clock source. An overrun error during reception can be detected. The transmit and receive units are configured with double buffering mechanism.
Section 18 Serial Communication Interface 4 (SCI4) 18.4.3 Data Transmission/Reception Before data transmission and reception, clear the TE and RE bits in SCR4 to 0 and then initialize as the following procedure of figure 18.3. Note: Before changing operating modes or communication format, the TE and RE bits must be cleared to 0. Clearing the TE bit to 0 sets the TDRE flag to 1. Note that clearing the RE bit to 0 does not affect the RDRF or ORER flag and the contents of RDR4.
Section 18 Serial Communication Interface 4 (SCI4) 18.4.4 Data Transmission Figure 18.4 shows an example flowchart of data transmission. Data transmission should be performed as the following procedure after the SCI4 initialization. Initialization [1] [1] Start transmission (TE = 1) Read TDRE in SCSR4 [2] [2] [3] TDRE = 1? No Pin SO4 functions as output pin for transmit data After reading SCSR4 and confirming TDRE = 1, write transmit data in TDR4.
Section 18 Serial Communication Interface 4 (SCI4) During transmission, the SCI4 operates as shown below. 1. The SCI4 sets the TE bit to 1 and clears the TDRE flag to 0 when transmit data is written to in TDR4 to transmit data from TDR4 to SR4. After that, the SCI4 sets the TDRE flag to 1 to start transmission. At this time, when the TIE bit in SCR4 is set to 1, a TXI is generated. 2. In clock output mode, the SCI4 outputs eight pulses of the synchronous clock.
Section 18 Serial Communication Interface 4 (SCI4) 18.4.5 Data Reception Figure 18.6 shows an example flowchart of data reception. Data reception should be performed as the following procedure after the SCI4 initialization.
Section 18 Serial Communication Interface 4 (SCI4) During reception, the SCI4 operates as shown below. 1. The SCI4 initialization is performed in synchronization with the synchronous clock input or output and starts reception. 2. The SCI4 stores received data from the LSB to MSB of SR4. 3. After reception, the SCI4 checks that RDRF = 0 and whether receive data is ready for being transferred from SR4 to RDR4. 4.
Section 18 Serial Communication Interface 4 (SCI4) 18.4.6 Simultaneous Data Transmission and Reception Figure 18.8 shows an example flowchart of simultaneous data transmission and reception. Simultaneous data transmission and reception should be performed as the following procedure after the SCI4 initialization.
Section 18 Serial Communication Interface 4 (SCI4) Notes: 1. When switching from transmission to simultaneous data transmission and reception, confirm that the SCI4 completes transmission and both the TDRE and TEND bits are set to 1. After that, clear the TE bit to 0 and then set both the TE and RE bits to 1. 2.
Section 18 Serial Communication Interface 4 (SCI4) 18.6 Usage Notes When using the SCI4, keep in mind the following. 18.6.1 Relationship between Writing to TDR4 and TDRE The TDRE flag in SCSR4 is a status flag that indicates that data to be transmitted has not been stored in TDR4. When writing data to TDR4, the TDRE flag is automatically cleared to 0. The TDRE flag is set to 1 when the SCI4 transfers data from TDR4 to SR4. Data is written to TDR4 regardless of the TDRE flag value.
Section 18 Serial Communication Interface 4 (SCI4) Number of transfer Frame 1 Frame 2 Frame 3 Data 1 Data 2 Data 3 Data 1 Data 2 RDRF RDR4 (A) RDR4 read (B) RDR4 read At the timing of (A), data 1 is read. At the timing of (B), data 2 is read. Figure 18.9 Relationship between Reading RDR4 and RDRF In this case, RDR4 must be read only once after confirming RDRF = 1. If reading RDR4 twice or more, store the read data in the RAM, and use the stored data.
Section 18 Serial Communication Interface 4 (SCI4) Rev. 2.00 Jul.
Section 19 14-Bit PWM Section 19 14-Bit PWM This LSI has an on-chip 14-bit pulse width modulator (PWM) with four channels. Connecting the PWM to the low-pass filter enables the PWM to be used as a D/A converter. The standard PWM or pulse-division type PWM can be selected by software. Figure 19.1 shows a block diagram of the 14-bit PWM. 19.
Section 19 14-Bit PWM 19.2 Input/Output Pins Table 19.1 shows the 14-bit PWM pin configuration. Table 19.
Section 19 14-Bit PWM 19.3.1 PWM Control Register (PWCR) PWCR selects the input clocks and selects whether the standard PWM or pulse-division type PWM is used. Bit Bit Name Initial Value R/W Description 7 to 3 All 1 Reserved These bits are always read as 1 and cannot be modified. 2 PWCRm2 0 W PWM Output Waveform Select Selects whether the standard PWM waveform or pulsedivision type PWM waveform is output.
Section 19 14-Bit PWM 19.3.2 PWM Data Register (PWDR) PWDR is a 14-bit write-only register. PWDR indicates the high-level width in one pulse period of the PWM waveform when the pulse-division type PWM is selected. When data is written to the lower 14 bits of PWDR, the contents are latched in the PWM waveform generator and the PWM waveform generation data is updated. PWDR is initialized to 0 and always read as H'FFFF. Writing to this register should be in a word unit. 19.4 Operation 19.4.
Section 19 14-Bit PWM 19.4.2 Setting for Pulse-Division Type PWM Operation When using the pulse-division type PWM, set the registers in this sequence: 1. In accord with the PWM channel to be used, set the PWM1, PWM2, PWM3, or PWM4 bit (the former two bits are in PMR9 and the latter two in PFCR) to 1 to specify the P90/PWM1, P91/PWM2, P92/IRQ4/PWM3, or P93/PWM4 pin, respectively, to function as a PWM output pin. 2. Set PWCR to select a conversion period. 3. Set the data for output waveform in PWDR.
Section 19 14-Bit PWM Table 19.2 Relationship between PWCR, PWDR and Output Waveform PWCRm Setting Value Tfn [tcyc] Minimum Variation Width [tcyc] PWCRm1 PWCRm0 One Conversion TH [tcyc] Period [tcyc] 0 0 16384 (PWDRm+64) × 1 256 1 0 1 32768 (PWDRm+64) × 2 512 2 1 0 65536 (PWDRm+64) × 4 1024 4 1 1 131072 (PWDRm+64) × 8 2048 8 Note: 19.4.4 m = 1 to 4, n = 1 to 64 Setting for Standard PWM Operation When using the standard PWM, set the registers in this sequence: 1.
Section 19 14-Bit PWM 19.4.5 PWM Operating States The states of PWM module registers in each operating mode are shown in table 19.3. Table 19.3 PWM Operating States Operating Mode Reset Active Sleep Subactive Subsleep Standby Module Standby PWCRm Reset Functioning Functioning Retained Retained Retained Retained Retained PWDRm Reset Functioning Functioning Retained Retained Retained Retained Retained Watch Note: m = 4 to 1 19.5 Usage Notes 19.5.
Section 19 14-Bit PWM Rev. 2.00 Jul.
Section 20 A/D Converter Section 20 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 20.1. 20.1 Features • 10-bit resolution • Input channels: Eight channels • High-speed conversion: 12.4 µs per channel (in 10-MHz operation) • Sample and hold function • Conversion start method A/D conversion can be started by software and external trigger.
Section 20 A/D Converter ADTRG AMR AN0 ADSR AN1 AN2 Internal data bus Multiplexer AN3 AN4 AN5 AVCC AN6 AN7 + Comparator Control logic - AVCC Reference voltage AVSS ADRR AVSS [Legend] AMR: ADSR: ADRR: IRRAD: A/D mode register A/D start register A/D result register A/D conversion end interrupt request flag Figure 20.1 Block Diagram of A/D Converter Rev. 2.00 Jul.
Section 20 A/D Converter 20.2 Input/Output Pins Table 20.1 shows the input pins used by the A/D converter. Table 20.
Section 20 A/D Converter 20.3.1 A/D Result Register (ADRR) ADRR is a 16-bit read-only register that stores the results of A/D conversion. The data is stored in the upper 10 bits of ADRR. ADRR can be read by the CPU at any time, but the ADRR value during A/D conversion is undefined. After A/D conversion is completed, the conversion result is stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial value of ADRR is undefined. ADRR should be read in word size.
Section 20 A/D Converter Bit Bit Name Initial Value R/W Description 3 CH3 0 R/W Channel Select 3 to 0 2 CH2 0 R/W Select the analog input channel. 1 CH1 0 R/W 00xx: No channel selected 0 CH0 0 R/W 0100: AN0 0101: AN1 0110: AN2 0111: AN3 1000: AN4 1001: AN5 1010: AN6 1011: AN7 11xx: Use prohibited The channel selection should be made while the ADSF bit is cleared to 0. [Legend] x: Don't care Rev. 2.00 Jul.
Section 20 A/D Converter 20.3.3 A/D Start Register (ADSR) ADSR starts and stops the A/D conversion. Bit Bit Name Initial Value R/W Description 7 ADSF 0 R/W When this bit is set to 1, A/D conversion is started. When conversion is completed, the converted data is set in ADRR and at the same time this bit is cleared to 0. If this bit is written to 0, A/D conversion can be forcibly terminated.
Section 20 A/D Converter 20.4.2 External Trigger Input Timing The A/D converter can also start A/D conversion by input of an external trigger signal. External trigger input is enabled at the ADTRG pin when the ADTSTCHG bit in PMRB is set to 1* and TRGE bit in AMR is set to 1. Then when the input signal edge designated in the ADTRGNEG bit in IEGR is detected at the ADTRG pin, the ADSF bit in ADSR will be set to 1, starting A/D conversion. Figure 20.2 shows the timing.
Section 20 A/D Converter 20.5 Example of Use An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 20.3 shows the operation timing. 1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. 2.
Idle A/D conversion starts A/D conversion (1) Set* Set* Note: * ↓ indicates instruction execution by software. ADRR Channel 1 (AN1) operating state ADSF IENAD Interrupt (IRRAD) A/D conversion result (1) ↓ Read conversion result Idle A/D conversion (2) Set* ↓ Read conversion result A/D conversion result (2) Idle Section 20 A/D Converter Figure 20.3 Example of A/D Conversion Operation Rev. 2.00 Jul.
Section 20 A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRR data Yes Perform A/D conversion? No End Figure 20.
Section 20 A/D Converter 20.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 20.6). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 20.7).
Section 20 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 20.6 A/D Conversion Accuracy Definitions (1) Digital output Full-scale error Ideal A/D conversion characterist Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 20.7 A/D Conversion Accuracy Definitions (2) Rev. 2.00 Jul.
Section 20 A/D Converter 20.7 Usage Notes 20.7.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less.
Section 20 A/D Converter 20.7.3 Other Usage Notes 1. ADRR should be read only when the ADSF bit in ADSR is cleared to 0. 2. Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. 3. When A/D conversion is started after clearing module standby mode, wait for 10φ clock cycles before starting A/D conversion. Rev. 2.00 Jul.
Section 21 LCD Controller/Driver Section 21 LCD Controller/Driver This LSI has an on-chip segment-type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 21.1 Features • Display capacity Duty Cycle Internal Driver Static 40 SEG 1/2 40 SEG 1/3 40 SEG 1/4 40 SEG • LCD RAM capacity 8 bits × 20 bytes (160 bits) • Word access to LCD RAM • The segment output pins can be used as ports. SEG40 to SEG1 pins can be used as ports in groups of four.
Section 21 LCD Controller/Driver Figure 21.1 shows a block diagram of the LCD controller/driver.
Section 21 LCD Controller/Driver 21.2 Input/Output Pins Table 21.1 shows the LCD controller/driver pin configuration. Table 21.1 Pin Configuration Name Symbol Segment output pins SEG40 to SEG1 Output Common output pins COM4 to COM1 Output LCD power supply pins V1, V2, V3 — Used when a bypass capacitor is connected externally, and when an external power supply circuit is used LCD step-up capacitance pins C1, C2 — Capacitance pins for stepping up the LCD drive power supply 21.
Section 21 LCD Controller/Driver 21.3.1 LCD Port Control Register (LPCR) LPCR selects the duty cycle, LCD driver, and pin functions. Bit Bit Name Initial Value R/W Description 7 DTS1 0 R/W Duty Cycle Select 1 and 0 6 DTS0 0 R/W Common Function Select 5 CMX 0 R/W The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty.
Section 21 LCD Controller/Driver Table 21.
Section 21 LCD Controller/Driver 21.3.2 LCD Control Register (LCR) LCR controls LCD drive power supply and display data, and selects the frame frequency. Bit Bit Name Initial Value R/W 7 — 1 — Description Reserved This bit is always read as 1 and cannot be modified. 6 PSW 0 R/W LCD Drive Power Supply Control Can be used to turn off the LCD drive power supply when LCD display is not required in power-down mode, or when an external power supply is used.
Section 21 LCD Controller/Driver Table 21.4 Frame Frequency Selection Frame Frequency* Bit 3: CKS3 Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Operating Clock φ = 2 MHz 0 x 0 0 φW 128 Hz* 1 φW/2 64 Hz* 2 64 Hz* 2 1 x φW/4 32 Hz* 2 32 Hz* 2 0 0 φ/2 — 244 Hz 1 φ/4 977 Hz 122 Hz 0 φ/8 488 Hz 61 Hz 1 φ/16 244 Hz 30.5 Hz 0 φ/32 122 Hz — 1 φ/64 61 Hz — 0 φ/128 30.
Section 21 LCD Controller/Driver 21.3.3 LCD Control Register 2 (LCR2) LCR2 controls switching between the A waveform and B waveform, selection of the step-up clock for the 3-V constant-voltage circuit, connection with the LCD power-supply split resistor, and turning on or off 3-V constant-voltage power supply. Bit Bit Name Initial Value R/W Description 7 LCDAB 0 R/W A Waveform/B Waveform Switching Control Specifies whether the A waveform or B waveform is used as the LCD drive waveform.
Section 21 LCD Controller/Driver 21.3.4 LCD Trimming Register (LTRMR) LTRMR adjusts the 3-V constant-voltage used for LCD drive power supply and the output voltage of 3-V constant-voltage power supply circuit.
Section 21 LCD Controller/Driver Bit Bit Name Initial Value R/W Description 2 CTRM2 0 R/W 1 CTRM1 0 R/W Variable Voltage Adjustment of 3-V Constant-Voltage 1 2 Power Supply* * 0 CTRM0 0 R/W The LCD drive power supply adjusted by the TRM bits can further be adjusted. If an LCD panel does not function normally due to a temperature in which LCD is used, set these bits to adjust it. 000: ±0 V 001: 0.09 V 010: 0.18 V 011: 0.27 V 100: -0.36 V 101: -0.27 V 110: -0.18 V 111: -0.09 V Note: 1.
Section 21 LCD Controller/Driver 21.3.5 BGR Control Register (BGRMR) BGRMR controls whether the band-gap reference circuit (BGR) which generates the reference voltage of the 3-V constant-voltage power supply operates or halts, and adjusts the reference voltage. Bit Bit Name Initial Value R/W 7 BGRSTPN 0 R/W Description Band-Gap Reference Circuit Control Controls whether the band-gap reference circuit operates or halts.
Section 21 LCD Controller/Driver 21.4 Operation 21.4.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. (1) Hardware Settings (a) Using 1/2 duty When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 21.2. VCC V1 V2 V3 VSS Figure 21.
Section 21 LCD Controller/Driver (c) LCD Drive Power Supply Setting With this LSI, there are two ways of providing LCD power: by using the on-chip power supply circuit, or by using an external power supply circuit. When an external power supply circuit is used for the LCD drive power supply, connect the external power supply to the V1 pin. (2) Software Settings (a) Duty Selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0.
Section 21 LCD Controller/Driver 21.4.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 21.3 to 21.6. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on.
Section 21 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 H'FFF360 SEG2 SEG2 H'FFF373 SEG40 COM3 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG1 SEG1 SEG1 SEG40 SEG40 SEG39 SEG39 SEG39 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 21.
Section 21 LCD Controller/Driver H'FFF360 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 Display space SEG40 H'FFF364 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 Space not used for display H'FFF373 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Figure 21.6 LCD RAM Map (Static Mode) Rev. 2.00 Jul.
Section 21 LCD Controller/Driver Figure 21.7 shows output waveforms for each duty cycle (A waveform).
Section 21 LCD Controller/Driver Figure 21.8 shows output waveforms for each duty cycle (B waveform).
Section 21 LCD Controller/Driver Table 21.5 shows output levels. Table 21.5 Output Levels Static 1/2 duty 1/3 duty 1/4 duty M: 21.4.
Section 21 LCD Controller/Driver Notes: 1. Power supply might be insufficient when a large panel is driven. In this case, use Vcc for power supply, or use an external power supply circuit. 2. Do not use a polarized capacitance such as an electrolytic capacitor for connection between the C1 pin and C2 pin. 3. A 3-V constant-voltage power supply circuit is turned on by SUSP bit regardless of the setting of the PSW bit. 4.
Section 21 LCD Controller/Driver Table 21.
Section 21 LCD Controller/Driver 21.4.5 Boosting LCD Drive Power Supply and Fine Adjustment When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case, the power supply impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 µF to pins V1 to V3, as shown in figure 21.10, or by adding a split resistor externally.
Section 21 LCD Controller/Driver 21.5 Usage Notes 21.5.1 Pin Handling when LCD Controller/Driver is not Used (1) V1, V2, and V3 Pins Connect these pins to the GND, though the CHG bit in LCR2 should not be changed from the initial value of 0. (The split resistor should be left disconnected.) (2) C1 and C2 Pins These pins should be left open. 21.5.2 Pin Handling when 3-V Constant-Voltage Power Supply Circuit is not Used The C1 and C2 pins should be left open. Rev. 2.00 Jul.
Section 21 LCD Controller/Driver Rev. 2.00 Jul.
Section 22 I2C Bus Interface 2 (IIC2) 2 Section 22 I C Bus Interface 2 (IIC2) 2 2 The I C bus interface 2 conforms to and provides a subset of the Philips I C bus (inter-IC bus) 2 interface functions. The register configuration that controls the I C bus differs partly from the 2 Philips configuration, however. Figure 22.1 shows a block diagram of the I C bus interface 2. Figure 22.2 shows an example of I/O pin connections to external circuits. 22.
Section 22 I2C Bus Interface 2 (IIC2) Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT SDA Output control SAR ICDRS Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt
Section 22 I2C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SDA in SCL SDA SDA out SCL in (Master) SCL out SCL SDA SCL out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 22.2 External Circuit Connections of I/O Pins 22.2 Input/Output Pins 2 Table 22.1 shows the input/output pins of the I C bus interface 2. Table 22.
Section 22 I2C Bus Interface 2 (IIC2) 22.3 Register Descriptions 2 The I C bus interface 2 has the following registers. • I C bus control register 1 (ICCR1) 2 • I C bus control register 2 (ICCR2) 2 • I C bus mode register (ICMR) 2 • I C bus interrupt enable register (ICIER) 2 • I C bus status register (ICSR) 2 • Slave address register (SAR) • I C bus transmit data register (ICDRT) 2 • I C bus receive data register (ICDRR) 2 • I C bus shift register (ICDRS) 2 22.3.
Section 22 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5 MST 0 R/W Master/Slave Select 4 TRS 0 R/W Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames.
Section 22 I2C Bus Interface 2 (IIC2) Table 22.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 Clock φ = 2 MHz φ = 5 MHz φ = 10 MHz 0 0 0 0 φ/28 71.4 kHz 179 kHz 357 kHz 1 φ/40 50.0 kHz 125 kHz 250 kHz 0 φ/48 41.7 kHz 104 kHz 208 kHz 1 φ/64 31.3 kHz 78.1 kHz 156 kHz 0 φ/80 25.0 kHz 62.5 kHz 125 kHz 1 φ/100 20.0 kHz 50.0 kHz 100 kHz 0 φ/112 17.9 kHz 44.6 kHz 89.3 kHz 1 φ/128 15.6 kHz 39.1 kHz 78.1 kHz 0 φ/56 35.7 kHz 89.
Section 22 I2C Bus Interface 2 (IIC2) 22.3.2 2 I C Bus Control Register 2 (ICCR2) ICCR1 issues start/stop conditions, handles the SDA pin, monitors the SCL pin, and controls reset 2 in the control part of the I C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode.
Section 22 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
Section 22 I2C Bus Interface 2 (IIC2) 22.3.3 2 I C Bus Mode Register (ICMR) ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Select 0: MSB-first 1: LSB-first 2 Set this bit to 0 when the I C bus format is used.
Section 22 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits 2 is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
Section 22 I2C Bus Interface 2 (IIC2) 22.3.4 2 I C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled.
Section 22 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W 4 NAKIE 0 R/W Description NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clock synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled.
Section 22 I2C Bus Interface 2 (IIC2) 22.3.5 2 I C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status.
Section 22 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W 4 NACKF 0 R/(W)* No Acknowledge Detection Flag Description [Setting condition] • No acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 Writing of 0 to bit NACKF after reading NACKF = 1 R/(W)* Stop Condition Detection Flag [Setting conditions] • In master mode, a stop condition is detected after frame transferred • In slave mode, the slave addre
Section 22 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W 1 AAS 0 R/(W)* Slave Address Recognition Flag Description In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR.
Section 22 I2C Bus Interface 2 (IIC2) 22.3.6 Slave Address Register (SAR) SAR selects the communication format and sets the slave address. When the chip is in slave mode 2 with the I C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Section 22 I2C Bus Interface 2 (IIC2) 22.4 Operation 2 2 The I C bus interface 2 can communicate either in I C bus mode or clock synchronous serial mode by setting the FS bit in the slave address register (SAR). 22.4.1 2 I C Bus Format 2 2 Figure 22.3 shows the I C bus formats. Figure 22.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits.
Section 22 I2C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 22.4.
Section 22 I2C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 2 Bit 7 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS Data 1 Address + R/W User processing [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 22.
Section 22 I2C Bus Interface 2 (IIC2) 22.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 22.7 and 22.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
Section 22 I2C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (Master output) SDA (Slave output) 9 1 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing [2] Read ICDRR (dummy read) TEND and TRS Figure 22.7 Master Receive Mode Operation Timing (1) Rev. 2.00 Jul.
Section 22 I2C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A/A SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR User processing Data n Data n-1 [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 22.8 Master Receive Mode Operation Timing (2) 22.4.
Section 22 I2C Bus Interface 2 (IIC2) Slave receive mode SCL (Master output) Slave transmit mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT ICDRS Data 1 Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 22.9 Slave Transmit Mode Operation Timing (1) Rev.
Section 22 I2C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) [5] Clear TDRE after clearing TRS Figure 22.10 Slave Transmit Mode Operation Timing (2) Rev. 2.00 Jul.
Section 22 I2C Bus Interface 2 (IIC2) 22.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 22.11 and 22.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1.
Section 22 I2C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 22.12 Slave Receive Mode Operation Timing (2) 22.4.
Section 22 I2C Bus Interface 2 (IIC2) (2) Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 22.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
Section 22 I2C Bus Interface 2 (IIC2) (3) Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 22.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
Section 22 I2C Bus Interface 2 (IIC2) 22.4.7 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 22.16 shows a block diagram of the noise canceller circuit. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Section 22 I2C Bus Interface 2 (IIC2) Start Initialize [1] Test the status of the SCL and SDA lines. [2] Set master transmit mode. [3] Issue the start condition. [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP. [3] [5] Wait for 1 byte to be transmitted. Write transmit data in ICDRT [4] [6] Test the acknowledge transferred from the specified slave device. [7] Set the second and subsequent bytes (except for the final byte) of transmit data.
Section 22 I2C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDRR.* [4] Wait for 1 byte to be received [5] Check whether it is the (last receive - 1). [6] Read the receive data. [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [8] Read the (final byte - 1) of receive data. [9] Wait for the last byte to be receive.
Section 22 I2C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. Read TDRE in ICSR [5] Wait for the last byte to be transmitted. [3] No TDRE=1 ? Yes Yes [6] Clear the TEND flag . [7] Set slave receive mode. Last byte? No [2] Set transmit data for ICDRT (except for the last data). [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag.
Section 22 I2C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? [4] Wait for 1 byte to be received. Yes No Read ICDRR [5] [8] Read the (last byte - 1) of receive data.
Section 22 I2C Bus Interface 2 (IIC2) 22.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun. Table 22.3 shows the contents of each interrupt request. Table 22.
Section 22 I2C Bus Interface 2 (IIC2) 22.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 22.21 shows the timing of the bit synchronous circuit and table 22.
Section 22 I2C Bus Interface 2 (IIC2) 22.7 Usage Notes 22.7.1 Note on Issuing Stop Condition and Start (Re-Transmit) Condition The stop condition or start (re-transmit) condition should be issued after recognizing the falling edge of the ninth clock. The falling edge of the ninth clock can be recognized by checking the 2 SCLO bit in the I C control register 2 (ICCR2).
Section 22 I2C Bus Interface 2 (IIC2) 22.7.4 Restriction on the Use of Bit Manipulation Instructions for MST and TRS Setting in Multimaster Operation In multimaster operation, if the master transmit is set with bit manipulation instructions in the order from the MST bit to the TRS bit, the AL bit in the ICSR register will be set to 1 but the master transmit mode (MST = 1, TRS = 1) may be set, depending on the arbitration lost timing.
Section 22 I2C Bus Interface 2 (IIC2) Rev. 2.00 Jul.
Section 23 Power-On Reset Circuit Section 23 Power-On Reset Circuit This LSI has an on-chip power-on reset circuit. A block diagram of the power-on reset circuit is shown in figure 23.1. 23.1 Feature • Power-on reset circuit An internal reset signal is generated at turning the power on by externally connecting a capacitor. Vcc φ Vcc CK R 3-bit counter COUT Rp RES R Voltage detector Q S Internal reset signal CRES Figure 23.1 Power-On Reset Circuit Rev. 2.00 Jul.
Section 23 Power-On Reset Circuit 23.2 Operation 23.2.1 Power-On Reset Circuit The operation timing of the power-on reset circuit is shown in figure 23.2. As the power supply voltage rises, the capacitor, which is externally connected to the RES pin, is gradually charged through the on-chip pull-up resistor (Rp). The low level of the RES pin is sent to the LSI and the whole LSI is reset. When the level of the RES pin reaches to the predetermined level, a voltage detection circuit detects it.
Section 24 Address Break Section 24 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit in CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 24 Address Break 24.1 Register Descriptions The address break has the following registers. • Address break control register 2 (ABRKCR2) • Address break status register 2 (ABRKSR2) • Break address register 2 (BAR2E, BAR2H, BAR2L) • Break data register 2 (BDR2H, BDR2L) 24.1.1 Address Break Control Register 2 (ABRKCR2) ABRKCR2 sets address break conditions.
Section 24 Address Break Bit Bit Name Initial Value R/W Description 1 DCMP21 0 R/W Data Compare Condition Select 1 and 0 0 DCMP20 0 R/W These bits set the comparison condition between the data set in BDR2 and the internal data bus.
Section 24 Address Break 24.1.2 Address Break Status Register 2 (ABRKSR2) ABRKSR2 consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W 7 ABIF2 0 R/W Description Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR2 is satisfied [Clearing condition] When 0 is written after ABIF2=1 is read 6 ABIE2 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
Section 24 Address Break 24.2 Operation When the ABIF2 and ABIE2 bits in ABRKSR2 are set to 1, the address break function generates an interrupt request to the CPU. The ABIF2 bit in ABRKSR2 is set to 1 by the combination of the address set in BAR2, the data set in BDR2, and the conditions set in ABRKCR2. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU.
Section 24 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR2 = H'A0 • BAR2 = H'00025A Program 000258 00025A * 00025C 000260 000262 : NOP NOP MOV.W @H'00025A,R0 * The address break condition is set NOP NOP Underline indicates the address : to be stacked.
Section 25 List of Registers Section 25 List of Registers The register list gives information on the on-chip register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) • Registers are listed from the lower allocation addresses. • Registers are classified by functional modules. • The data bus width is indicated. • The number of access states is indicated. 2.
Section 25 List of Registers 25.1 Register Addresses (Address Order) The data bus width indicates the number of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Register Name Abbreviation Bit No.
Section 25 List of Registers Register Name Abbreviation Bit No.
Section 25 List of Registers Abbreviation Bit No.
Section 25 List of Registers Register Name Abbreviation Bit No.
Section 25 List of Registers Register Name Abbreviation Bit No.
Section 25 List of Registers Register Name Abbreviation Bit No.
Section 25 List of Registers Register Name Abbreviation Bit No. Address* Data Bus Access Module Name Width State Interrupt request register 2 IRR2 8 H'FFF7 Interrupts 8 2 Wakeup interrupt request register IWPR 8 H'FFF9 Interrupts 8 2 Clock halt register 1 CKSTPR1 8 H'FFFA SYSTEM 8 2 Clock halt register 2 CKSTPR2 8 H'FFFB SYSTEM 8 2 Clock halt register 3 CKSTPR3 8 H'FFFC SYSTEM 8 2 Notes: 1. 2. 3. 4. Indicates the lower 16-bit address.
Section 25 List of Registers 25.2 Register Bits Register bit names of the on-chip peripheral modules are described below.
Section 25 List of Registers Register Abbreviation Bit 7 TGRB_1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TPU_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWCR3 PWCR32 PWCR31 PWCR30 PWDR3 PWDR313 PWDR312 PWDR311 PWDR310 PWDR39 PWDR38 PWDR37 PWDR36 PWDR35 PWDR34 PWDR33 PWDR32 PWDR31 PWDR30 TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_2 MD1 MD0 TIOR_2 IOB
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name ICMR MLS WAIT BCWP BC2 BC1 BC0 IIC2 ICIER TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ SAR SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS ICDRT ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 ICDRR ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 IPRA IPRA7 IPRA6 IPRA5 IPRA4 IPRA
Section 25 List of Registers Register Abbreviation Bit 7 ECPWDR Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9 ECPWDR8 Module Name 1 AEC* ECPWDR7 ECPWDR6 ECPWDR5 ECPWDR4 ECPWDR3 ECPWDR2 ECPWDR1 ECPWDR0 WEGR WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Interrupts SPCR SPC32 SPC31 SCINV3 SCINV2 SCINV1 SCINV0 SCI3 AEGSR AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME ECCR ACKH1 ACKH0 ACKL1 ACK
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TCWD TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 WDT*2 TMC TMC7 TMC6 TMC5 TMC3 TMC2 TMC1 TMC0 Timer C TCC/TLC TCC7/ TCC6/ TCC5/ TCC4/ TCC3/ TCC2/ TCC1/ TCC0/ TLC7 TLC6 TLC5 TLC4 TLC3 TLC2 TLC1 TLC0 TCRF TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 TCSRF OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL TCFH TCFH7 TCFH6 TCFH5 TCFH4 TCFH3
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name I/O ports PDR1 P16 P15 P14 P13 P12 P11 P10 PDR3 P37 P36 P32 P31 P30 PDR4 P42 P41 P40 PDR5 P57 P56 P55 P54 P53 P52 P51 P50 PDR6 P67 P66 P65 P64 P63 P62 P61 P60 PDR7 P77 P76 P75 P74 P73 P72 P71 P70 PDR8 P87 P86 P85 P84 P83 P82 P81 P80 PDR9 P93 P92 P91 P90 PDRA PA3 PA2 PA1 PA0 PD
Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Interrupts IENR2 IENDT IENAD IENTG IENTFH IENTFL IENTC IENEC INTM INTM1 INTM0 IRR1 IRR4 IRR3 IRREC2 IRRI1 IRRI0 IRR2 IRRDT IRRAD IRRTG IRRTFH IRRTFL IRRTC IRREC IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 S4CK ADCKSTP CKSTPR1 S31CK S32CK STP* STP STP IICCKSTP PW2CK 3 CKSTPR2 CKSTPR3 Notes: 1. 2. 3. 4.
Section 25 List of Registers 25.
Section 25 List of Registers Register Abbreviation Reset Active Sleep Watch Subactive Subsleep Standby Module TCR_2 Initialized TPU_2 TMDR_2 Initialized TIOR_2 Initialized TIER_2 Initialized TSR_2 Initialized TCNT_2 Initialized TGRA_2 Initialized TGRB_2 Initialized PWCR4 Initialized PWDR4 Initialized R
Section 25 List of Registers Register Abbreviation Reset Active Sleep Watch Subactive Subsleep Standby Module IPRD Initialized Interrupts IPRE Initialized IPRF Initialized SMR3_3 Initialized Initialized Initialized BRR3_3 Initialized Initialized Initialized SCR3_3 Initialized Initialized Initialized TDR3_3 Initialized Initialized Initialized SSR3_3 Initialized Initialized
Section 25 List of Registers Register Abbreviation Reset Active Sleep Watch TDR3_1 Initialized Initialized SSR3_1 Initialized Initialized RDR3_1 Initialized LPCR Initialized LCR Initialized LCR2 Subactive Subsleep Standby Module Initialized SCI3_1 Initialized Initialized Initialized Initialized LTRMR Initialized BGRMR Initialized SEMR Initialized I
Section 25 List of Registers Register Abbreviation Reset Active Sleep Watch Subactive Subsleep Standby Module PMR1 Initialized I/O ports OSCCR Initialized Clock pulse generator PMR3 Initialized I/O ports PMR4 Initialized PMR5 Initialized PMR9 Initialized PMRB Initialized PFCR Initialized SPCR2 Initialized SCI3 PWCR2 I
Section 25 List of Registers Register Abbreviation Reset Active Sleep Watch Subactive Subsleep Standby Module PCR3 Initialized I/O ports PCR4 Initialized PCR5 Initialized PCR6 Initialized PCR7 Initialized PCR8 Initialized PCR9 Initialized PCRA Initialized PCRC Initialized SYSCR1 Initialized SYSCR2 Ini
Section 25 List of Registers Rev. 2.00 Jul.
Section 26 Electrical Characteristics Section 26 Electrical Characteristics 26.1 Absolute Maximum Ratings for F-ZTAT Version Table 26.1 lists the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +4.3 V * Analog power supply voltage AVCC –0.3 to +4.3 V Input voltage Other than port B Vin –0.3 to VCC +0.3 V Port B AVin –0.3 to AVCC +0.
Section 26 Electrical Characteristics 26.2 Electrical Characteristics for F-ZTAT Version 26.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. (1) System clock oscillator selected (10-MHz version) fW (kHz) fosc (MHz) 10.0 38.4 32.768 2.0 1.8 2.7 3.6 Vcc (V) 2.7 3.6 Vcc (V) 1.
Section 26 Electrical Characteristics (3) On-chip oscillator for system clock selected Rosc used (reference value) fW (kHz) fosc (MHz) 10.0 38.4 32.768 0.5 1.8 2.7 3.6 Vcc (V) • Active (high-speed) mode • Sleep (high-speed) mode 1.8 2.7 3.6 Vcc (V) • All operating modes • Refer to note Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation stabilization time has elapsed after switching on. Figure 26.
Section 26 Electrical Characteristics (1) System clock oscillator selected (10-MHz version) 10.0 φ (MHz) φSUB (kHz) 19.2 16.384 9.6 8.192 4.2 4.8 4.096 2.0 1.8 2.7 3.6 Vcc (V) • Active (high-speed) mode • Sleep (high-speed) mode (other than CPU) 1.8 2.7 3.6 Vcc (V) • Subactive mode • Subsleep mode (other than CPU) • Watch mode (other than CPU) φ (kHz) 1250 525 31.25 1.8 2.7 3.6 Vcc (V) • Active (medium-speed) mode • Sleep (medium-speed) mode (other than CPU) Figure 26.
Section 26 Electrical Characteristics φ SUB (kHz) (2) System clock oscillator selected (4-MHz version) 19.2 16.384 9.6 10.0 φ (MHz) 8.192 4.2 4.8 4.096 2.0 1.8 2.7 3.6 Vcc (V) • Active (high-speed) mode • Sleep (high-speed) mode (other than CPU) 1.8 2.7 3.6 Vcc (V) • Subactive mode • Subsleep mode (other than CPU) • Watch mode (other than CPU) 1250 φ (kHz) 525 31.25 1.8 2.7 3.6 Vcc (V) • Active (medium-speed) mode • Sleep (medium-speed) mode (other than CPU) Figure 26.
Section 26 Electrical Characteristics (3) On-chip oscillator for system clock selected φ (MHz) Rosc used (reference value) φ SUB (kHz) 19.2 16.384 9.6 8.192 4.8 10.0 4.096 0.5 1.8 2.7 3.6 Vcc (V) • Active (high-speed) mode • Sleep (high-speed) mode (other than CPU) 1.8 2.7 3.6 Vcc (V) • Subactive mode • Subsleep mode (other than CPU) • Watch mode (other than CPU) Rosc used (reference value) φ (kHz) 1250 7.8125 1.8 2.7 3.
Section 26 Electrical Characteristics (1) System clock oscillator selected (10-MHz version) φ (MHz) 10.0 4.2 2.0 1.8 2.7 3.6 AVcc (V) • Active (high-speed) mode • Sleep (high-speed) mode (2) System clock oscillator selected (4-MHz version) φ (MHz) 10.0 4.2 2.0 1.8 2.7 3.6 AVcc (V) • Active (high-speed) mode • Sleep (high-speed) mode Figure 26.
Section 26 Electrical Characteristics 26.2.2 DC Characteristics Table 26.2 lists DC characteristics. Table 26.2 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Item Input high voltage Test Condition Symbol Applicable Pins VIH RES, TEST, NMI* , WKP0 to WKP7, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK33, SCK32, SCK31, SCK4 Max. Unit 0.9 VCC VCC + 0.3 V IRQ0*5, IRQ1*5, IRQ3*5 0.9 VCC AVCC + 0.
Section 26 Electrical Characteristics Item Input low voltage Symbol Applicable Pins VIL Test Condition Values Min. Typ. Max. Unit RES, TEST, NMI* , WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK33, SCK32, SCK31, SCK4 –0.3 0.1 VCC V RXD33, RXD32, RXD31, IrRXD, UD –0.3 0.2 VCC V OSC1 –0.3 0.1 VCC V X1 –0.3 0.
Section 26 Electrical Characteristics Item Symbol Output high voltage VOH Output low VOL voltage Test Applicable Pins Condition Values Min. Typ. Max. Unit V P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3 –IOH = 1.0 mA VCC = 2.7 to 3.6 V VCC – 1.0 –IOH = 0.1 mA VCC – 0.3 P90 to P93 IOH = 1.0mA VCC = 2.7 to 3.6 V VCC – 1.0 IOH = 0.1 mA VCC – 0.
Section 26 Electrical Characteristics Item Test Symbol Applicable Pins Condition Input/output IIL leakage current Pull-up MOS current –Ip Input CIN capacitance Values Min. Typ. Max. Unit µA TEST, NMI* , OSC1, X1, P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3, P90 to P93 VIN = 0.5 V to VCC – 0.5 V 1.0 PB0 to PB7 VIN = 0.5 V to AVCC – 0.5 V 1.
Section 26 Electrical Characteristics Item Test Symbol Applicable Pins Condition Active mode IOPE1 supply current IOPE2 Sleep mode ISLEEP supply current VCC VCC VCC Rev. 2.00 Jul. 04, 2007 Page 558 of 692 REJ09B0309-0200 Values Min. Typ. Max. Unit Note Active (high-speed) mode, VCC = 1.8 V, fOSC = 2 MHz 1.1 Max. guideline = 1.1 × typ *1 *2 *4 Active (high-speed) mode, VCC = 3.0 V, fOSC = Rosc 3.7 Max. guideline = 1.1 × typ *1 *2 Active (high-speed) mode, VCC = 3.
Section 26 Electrical Characteristics Item Test Symbol Applicable Pins Condition Subactive ISUB mode supply current VCC Values Min. Typ. Max. Unit Note VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator used (φSUB = φW/8) 9 *1 *2 Reference value VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator used (φSUB = φW/2) 27 50 µA *1 *2 Subsleep ISUBSP mode supply current VCC VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator used (φSUB = φW/2) 5.5 9.
Section 26 Electrical Characteristics Values Test Symbol Applicable Pins Condition Min. Typ. Max. Unit Allowable output low current (per pin) IOL Output pins except port 9 0.5 P90 to P93 15.0 Allowable output low current (total) ΣIOL Output pins except port 9 20.0 Port 9 60.0 Allowable output high current (per pin) –IOH Vcc = 2.7 to 3.6 V 2.0 Vcc = 1.8 to 3.6 V 0.2 Allowable output high current (total) Σ – IOH 10.
Section 26 Electrical Characteristics 2. 3. 4. 5. Excludes current in pull-up MOS transistors and output buffers. Used for the determination of user mode or boot mode when the reset is released. Only for 4-MHz version. When IRQ0, IRQ1, and IRQ3 in PMRB are set to 0, and IRQ0, IRQ1, and IRQ3 in PMRE are set to 1, the maximum value is VCC + 0.3 (V). Rev. 2.00 Jul.
Section 26 Electrical Characteristics 26.2.3 AC Characteristics Table 26.3 lists the control signal timing, table 26.4 lists the serial interface timing, and table 26.5 2 lists the I C bus interface timing. Table 26.3 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Section 26 Electrical Characteristics Item Subclock oscillation frequency Applicable Symbol Pins Values Test Condition Min. Typ. Max. Unit Reference Figure fW X1, X2 — 32.768 — or 38.4 kHz Watch clock (φW) tW cycle time X1, X2 — 30.5 or — 26.0 µs Figure 26.14 2 — 8 tW *1 2 — — tcyc tsubcyc Ceramic resonator — (Vcc = 2.2 to 3.6 V) 20 45 µs Ceramic resonator (other than above) — 80 — Crystal resonator (VCC = 2.7 to 3.6 V) — 0.8 2.0 Crystal resonator (VCC = 2.2 to 3.
Section 26 Electrical Characteristics Item External clock low width Applicable Symbol Pins tCPL Values Min. Typ. Max. Unit VCC = 2.7 to 3.6 V (10-MHz version) 40 — — ns VCC = 1.8 to 3.6 V (4-MHz version) 95 — — — 15.26 or 13.02 — µs VCC = 2.7 to 3.6 V (10-MHz version) — — 10 ns Figure 26.14 VCC = 1.8 to 3.6 V (4-MHz version) — — 24 — — 55.0 VCC = 2.7 to 3.6 V (10-MHz version) — — 10 ns Figure 26.14 VCC = 1.8 to 3.6 V (4-MHz version) — — 24 X1 — — 55.
Section 26 Electrical Characteristics Item Input pin high width Applicable Symbol Pins tIH Input pin low width tIL TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2 TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2 Min. Typ. Max. Unit 2 — tcyc — tsubcyc VCC = 2.7 to 3.6 V (10-MHz version) 50 — — VCC = 1.8 to 3.6 V (4-MHz version) 110 — — Single edge specified 1.5 — — Both edges specified 2.
Section 26 Electrical Characteristics Item Applicable Symbol Pins Values Test Condition UD pin minimum UD transition width Min. Typ. Max. Unit Reference Figure 4 — tcyc tsubcyc Figure 26.21 — Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2. For details on the power-on reset characteristics, refer to table 26.8 and figure 26.18. 3. The specifications may vary due to the effects of temperature, power-supply voltage, and dispersion of product lots.
Section 26 Electrical Characteristics 2 Table 26.5 I C Bus Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified. Item Symbol Test Condition Values Min. Typ. Max.
Section 26 Electrical Characteristics 26.2.4 A/D Converter Characteristics Table 26.6 lists the A/D converter characteristics. Table 26.6 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Item Symbol Applicable Pins Analog power supply voltage AVCC Analog input voltage Analog power supply current Values Test Condition Min. Typ. Max. Unit Notes AVCC 1.8 — 3.6 V AVIN AN0 to AN7 –0.3 — AVCC + 0.3 V AIOPE AVCC — — 1.
Section 26 Electrical Characteristics Item Conversion time Symbol Applicable Pins Values Test Condition Min. Typ. Max. Unit Notes AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V 12.4 — 124 µs System clock oscillator selected 7.8 15.5 31 µs On-chip oscillator for system clock selected Reference value (fRosc = 4 MHz) 29.5 — 124 µs System clock oscillator selected 31 62 124 µs On-chip oscillator for system clock selected Reference value (fRosc = 1 MHz) Other than AVCC = 2.7 to 3.
Section 26 Electrical Characteristics 26.2.5 LCD Characteristics Table 26.7 shows the LCD characteristics. Table 26.7 LCD Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Values Applicable Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes Segment driver drop VDS SEG1 to ID = 2 µA — — 0.6 V *1 SEG40 V1 = 2.7 to 3.6 V COM1 to ID = 2 µA — — 0.3 V *1 COM4 V1 = 2.7 to 3.6 V 1.5 3.0 7.0 MΩ 2.2 — 3.
Section 26 Electrical Characteristics 26.2.6 Power-On Reset Circuit Characteristics Table 26.8 Power-On Reset Circuit Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −20 to +75°C (regular specifications), Ta = −40 to +85°C (wide-range specifications), unless otherwise specified. Values Item Test Symbol Condition Min. Typ. Max. Unit Reference Figure Reset voltage V_rst 0.7VCC 0.8VCC 0.9VCC V Figure 23.
Section 26 Electrical Characteristics 26.2.7 Watchdog Timer Characteristics Table 26.9 Watchdog Timer Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −20 to +75°C (regular specifications), Ta = −40 to +85°C (wide-range specifications), unless otherwise specified. Item Symbol On-chip watchdog timer oscillator overflow time tovf Note: * Applicable Pins Test Condition Values Min. Typ. Max. Item Notes 0.2 0.
Section 26 Electrical Characteristics 26.2.8 Flash Memory Characteristics Table 26.10 lists the flash memory characteristics. Table 26.10 Flash Memory Characteristics Condition A: AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 3.6 V (operating voltage range in reading), VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing), Ta = –20 to +75°C (operating temperature range in programming/erasing: regular specifications, wide-range specifications) Condition B: AVCC = 1.8 V to 3.
Section 26 Electrical Characteristics Values Item Programming Erase Symbol Test Condition Min. Typ. Max.
Section 26 Electrical Characteristics 5. Set the maximum programming count (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (tP (max.)). The wait time after setting P bit (z1, z2) should be changed as follows according to the value of the programming count (n). Programming count (n) 1≤n≤6 z1 = 30 µs 7 ≤ n ≤ 1000 z2 = 200 µs 6. Erasing time maximum value (tE (max.)) = wait time after setting E bit (z) × maximum erasing count (N) 7.
Section 26 Electrical Characteristics 26.4 Electrical Characteristics for Masked ROM Version 26.4.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. (1) System clock oscillator selected fosc (MHz) 10.0 4.2 2.0 1.8 2.7 3.6 Vcc (V) • Active (high-speed) mode • Sleep (high-speed) mode (other than CPU) Figure 26.
Section 26 Electrical Characteristics (1) System clock oscillator selected 10.0 φ (MHz) φSUB (kHz) 19.2 16.384 9.6 8.192 4.2 4.8 4.096 2.0 1.8 2.7 3.6 Vcc (V) • Active (high-speed) mode • Sleep (high-speed) mode (other than CPU) 1.8 2.7 3.6 Vcc (V) • Subactive mode • Subsleep mode (other than CPU) • Watch mode (other than CPU) 1250 φ (kHz) 525 31.25 1.8 2.7 3.6 Vcc (V) • Active (medium-speed) mode • Sleep (medium-speed) mode (other than CPU) Figure 26.
Section 26 Electrical Characteristics φ SUB (kHz) (2) On-chip oscillator for system clock selected Rosc used (reference value) 19.2 16.384 9.6 φ (MHz) 8.192 10.0 4.8 4.096 0.5 1.8 2.7 3.6 Vcc (V) • Active (high-speed) mode • Sleep (high-speed) mode 1.8 2.7 3.6 Vcc (V) • Subactive mode • Subsleep mode (other than CPU) • Watch mode (other than CPU) φ (kHz) Rosc used (reference value) 1250 7.8125 1.8 2.7 3.6 Vcc (V) • Active (medium-speed) mode • Sleep (medium-speed) mode Figure 26.
Section 26 Electrical Characteristics (2) On-chip oscillator for system clock selected φ (MHz) Rosc used (reference value) 10.0 0.5 1.8 2.7 3.6 AVcc (V) • Active (high-speed) mode • Sleep (high-speed) mode Figure 26.13 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2) Rev. 2.00 Jul.
Section 26 Electrical Characteristics 26.4.2 DC Characteristics Table 26.12 lists the DC characteristics. Table 26.12 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Item Symbol Applicable Pins Input high voltage VIH Values Min. Typ. Max. Unit RES, TEST, NMI, WKP0 to WKP7, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK33, SCK32, SCK31 0.9 VCC — IRQ0∗4, IRQ1∗4, IRQ3∗4 0.9 VCC — AVCC + 0.3 V RXD33, RXD32, RXD31, IrRXD, UD 0.
Section 26 Electrical Characteristics Item Symbol Applicable Pins Input low voltage VIL Test Condition Values Min. Unit RES, TEST, NMI, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK33, SCK32, SCK31 –0.3 — 0.1VCC V RXD33, RXD32, RXD31, IrRXD, UD –0.3 — 0.2VCC V OSC1 –0.3 — 0.1VCC V X1 –0.3 — 0.
Section 26 Electrical Characteristics Item Symbol Applicable Pins Output high voltage VOH Output low VOL voltage Values Min. Unit P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3 –IOH = 1.0 mA VCC = 2.7 to 3.6V VCC – 1.0 — — –IOH = 0.1 mA VCC – 0.3 — — P90 to P93 –IOH = 1.0 mA VCC = 2.7 to 3.6V VCC – 1.0 — — –IOH = 0.1 mA VCC – 0.
Section 26 Electrical Characteristics Item Symbol Input/output | IIL | leakage current Pull-up MOS current –Ip Input CIN capacitance Applicable Pins Test Condition Values Min. Unit TEST, NMI, OSC1, X1, P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3, P90 to P93 VIN = 0.5 V to VCC – 0.5 V — — 1.0 PB0 to PB7 VIN = 0.5 V to AVCC – 0.5 V — — 1.
Section 26 Electrical Characteristics Item Symbol Applicable Pins Active mode IOPE1 supply current IOPE2 Sleep mode ISLEEP supply current VCC VCC VCC Rev. 2.00 Jul. 04, 2007 Page 584 of 692 REJ09B0309-0200 Test Condition Values Min. Unit Note Active (high-speed) mode, VCC = 1.8 V, fOSC = 2 MHz — 0.7 — Active (high-speed) mode, VCC = 3.0 V, fOSC = ROSC — 2.2 — Max. guideline = 1.1 × typ.*1 *2 Active (high-speed) mode, VCC = 3.0 V, fOSC = 4 MHz — 2.6 — Max. guideline = 1.1 × typ.
Section 26 Electrical Characteristics Item Test Symbol Applicable Pins Condition Subactive ISUB mode supply current VCC Values Min. Unit Note µA VCC = 1.8 V, LCD lighting, 32-kHz crystal resonator (φSUB = φW/2) — 6.5 — Reference value *1 *2 VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator (φSUB = φW/8) — 5.5 — Reference value *1 *2 VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator (φSUB = φW/2) — 11 17 *1 *2 Subsleep ISUBSP mode supply current VCC VCC = 2.
Section 26 Electrical Characteristics Values Test Symbol Applicable Pins Condition Min. RAM data retaining voltage VRAM VCC 1.5 — — V Permissible output low current (per pin) IOL Output pins except port 9 — — 0.5 mA P90 to P93 — — 15.0 Permissible output low current (total) ΣIOL Output pins except port 9 — — 20.0 Port 9 — — 60.0 Permissible output high current (per pin) –IOH Vcc = 2.7 to 3.6 V — — 2.0 Vcc = 1.8 to 3.6 V — — 0.
Section 26 Electrical Characteristics Mode RES Pin Internal State Other Pins Standby mode VCC CPU and timers both stop VCC On-chip WDT oscillator is off 32KSTOP = 1 Oscillator Pins System clock oscillator: Crystal resonator Subclock oscillator: Crystal resonator 2. Excludes current in pull-up MOS transistors and output buffers. 3. When IRQ0, IRQ1, and IRQ3 in PMRB are set to 0, and IRQ0, IRQ1, and IRQ3 in PMRE are set to 1, the maximum value is VCC + 0.3 (V). Rev. 2.00 Jul.
Section 26 Electrical Characteristics 26.4.3 AC Characteristics Table 26.13 lists the control signal timing, table 26.14 lists the serial interface timing, and table 2 26.15 lists the I C bus interface timing. Table 26.13 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Item Applicable Symbol Pins Values Min. Typ. Max. Unit OSC1, OSC2 VCC = 2.7 to 3.6 V 2.0 — 10.0 MHz VCC = 1.8 to 3.6 V 2.0 — 4.
Section 26 Electrical Characteristics Item Applicable Symbol Pins Values Test Condition Min. Typ. Max. Unit Reference Figure fW X1, X2 — 32.768 — or 38.4 kHz Watch clock (φW) tW cycle time X1, X2 — 30.5 or — 26.0 µs Figure 26.14 2 — 8 tW *1 2 — — tcyc tsubcyc OSC1, OSC2 Ceramic resonator — (Vcc = 2.2 to 3.6 V) 20 45 µs Ceramic resonator — (Other than above) 80 — Crystal resonator — (Vcc = 2.7 to 3.6 V) 0.8 2.0 Crystal resonator — (Vcc = 2.2 to 3.6 V) 1.2 3.
Section 26 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition External clock low width tCPL Typ. Max. Unit VCC = 2.7 to 3.6 V 40 — — ns VCC = 1.8 to 3.6 V 95 — — 15.26 or 13.02 — µs VCC = 2.7 to 3.6 V — — 10 ns VCC = 1.8 to 3.6 V — — 24 — — 55.0 ns VCC = 2.7 to 3.6 V — — 10 ns VCC = 1.8 to 3.6 V — — 24 X1 — — 55.0 ns OSC1 X1 External clock rising time tCPr OSC1 — X1 External clock falling time tCPf OSC1 Min.
Section 26 Electrical Characteristics Item Input pin low width Applicable Symbol Pins tIL UD pin minimum UD transition width Test Condition IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG AEVL, AEVH tTCKWL Values TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2 Min. Typ. Max. Unit 2 — — tcyc tsubcyc VCC = 2.7 to 3.6 V 50 — — VCC = 1.8 to 3.6 V 110 — — Single edge specified 1.5 — — Both edges specified 2.5 — — 4 — — Reference Figure Figure 26.
Section 26 Electrical Characteristics Table 26.14 Serial Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified. Values Item Input clock cycl Asynchronous Symbol Test Condition Min. Typ. Max. Unit Reference Figure tscyc 4 — — 6 — — tcyc or tsubcyc Figure 26.17 Clock synchronous Input clock pulse width tSCKW 0.4 — 0.6 tscyc Figure 26.17 Transmit data delay time (clock synchronous) tTXD — — 1 tcyc or tsubcyc Figure 26.
Section 26 Electrical Characteristics 2 Table 26.15 I C Bus Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified. Values Item Symbol Test Condition Min. Typ. Max.
Section 26 Electrical Characteristics 26.4.4 A/D Converter Characteristics Table 26.16 lists the A/D converter characteristics. Table 26.16 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Values Applicable Symbol Pins Test Condition Min. Typ. Max. Unit Note Analog power supply voltage AVCC AVCC 1.8 — 3.6 V *1 Analog input voltage AVIN AN0 to AN7 –0.3 — AVCC + 0.3 V Analog power supply current AIOPE AVCC — — 1.
Section 26 Electrical Characteristics Item Conversion time Applicable Symbol Pins Test Condition AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V Other than AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V Values Min. Typ. Max. Unit Note 12.4 — 124 µs System clock oscillator selected 7.8 15.5 31 µs On-chip oscillator for system clock selected Reference value (fRosc = 4 MHz) 29.
Section 26 Electrical Characteristics 26.4.5 LCD Characteristics Table 26.17 shows the LCD characteristics. Table 26.17 LCD Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Values Applicable Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes Segment driver drop VDS SEG1 to ID = 2 µA — — 0.6 V *1 SEG40 V1 = 2.7 V to 3.6 V COM1 to ID = 2 µA — — 0.3 V *1 COM4 V1 = 2.7 V to 3.6 V 1.5 3.0 7.0 MΩ 2.2 — 3.
Section 26 Electrical Characteristics 26.4.6 Power-On Reset Circuit Characteristics Table 26.18 Power-On Reset Circuit Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −20 to +75°C (general specifications), Ta = −40 to +85°C (wide temperature range specifications), unless otherwise specified. Values Test Symbol Condition Min. Typ. Max. Unit Reference Figure Reset voltage V_rst 0.7VCC 0.8VCC 0.9VCC V Figure 23.
Section 26 Electrical Characteristics 26.5 Operation Timing Figures 26.14 to 26.21 show operation timings. tOSC, tW V IH OSC1 X1 V IL t CPH t CPL t CPr t CPf Figure 26.14 Clock Input Timing RES V IL t REL Figure 26.15 RES Low Width Timing NMI, IRQ0, IRQ1, V IRQ3, IRQ4, TMIC, TMIF, TMIG, ADTRG, V IH IL WKP0 to WKP7, IRQAEC, t AEVL, AEVH IL t IH Figure 26.16 Input Timing Rev. 2.00 Jul.
Section 26 Electrical Characteristics t SCKW SCK31 SCK32 SCK33 t scyc Figure 26.17 SCK3 Input Clock Timing t scyc SCK31 VIH or VOH* SCK32 SCK33 V or V * IL OL t TXD TXD31 TXD32 TXD33 (transmit data) VOH* VOL* t RXS t RXH RXD31 RXD32 RXD33 (receive data) Note: * Output timing reference levels Output high VOH = 1/2 Vcc + 0.2 V Output low VOL = 0.8 V See figure 26.22 for load conditions. Figure 26.18 SCI3 Input/Output Timing in Clock Synchronous Mode Rev. 2.00 Jul.
Section 26 Electrical Characteristics TCLKA to TCLKC tTCKWH tTCKWL Figure 26.19 Clock Input Timing for TCLKA to TCLKC Pins VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL P* tSDAS tSr tSCL tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 26.20 I C Bus Interface Input/Output Timing VIH UD VIL tUDL tUDH Figure 26.21 UD Pin Minimum Transition Width Timing Rev. 2.00 Jul.
Section 26 Electrical Characteristics 26.6 Output Load Circuit VCC 2.4 kΩ LSI output pin 30 pF 12 kΩ Figure 26.22 Output Load Condition Rev. 2.00 Jul.
Section 26 Electrical Characteristics 26.7 Recommended Resonators (1) Recommended Crystal Resonators Frequency (MHz) Manufacturer Product Type 4.194304 10 NIHON DEMPA KOGYO CO.,LTD. NR-18 NR-18 NIHON DEMPA KOGYO CO.,LTD. (2) Recommended Ceramic Resonators Frequency (MHz) 2 4.19 Manufacturer Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. 10 Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd.
Appendix Appendix A. Instruction Set A.
Appendix Symbol Description ¬ NOT (logical complement) ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Symbol Description ↔ Condition Code Notation (cont) Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev. 2.00 Jul.
Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Condition Code MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
Appendix No. of States*1 Condition Code — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — 0 — 0 — POP POP.W Rn W 2 @SP → Rn16 SP+2 → SP — — POP.L ERn L 4 @SP → ERn32 SP+4 → SP — — 0 — PUSH PUSH.W Rn W 2 SP–2 → SP Rn16 → @SP — — 0 — PUSH.
Appendix 2. Arithmetic Instructions No. of States*1 Condition Code Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 2 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
Appendix No. of States*1 Condition Code Advanced V C ERd32–1 → ERd32 — — L 2 ERd32–2 → ERd32 — — ↔ ↔ — 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ 2 DEC.L #2, ERd ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXU DIVXU. B Rs, Rd DIVXU.
Appendix No. of States*1 Condition Code W 2 0–Rd16 → Rd16 — NEG.L ERd L 2 0–ERd32 → ERd32 — EXTU EXTU.W Rd W 2 0 → ( of Rd16) — — 0 EXTU.L ERd L 2 0 → ( of ERd32) — — 0 EXTS EXTS.W Rd W 2 ( of Rd16) → ( of Rd16) — — EXTS.L ERd L 2 ( of ERd32) → ( of ERd32) — — Advanced ↔ ↔ ↔ NEG.W Rd Normal C ↔ ↔ ↔ — ↔ ↔ ↔ V ↔ ↔ ↔ ↔ 0–Rd8 → Rd8 2 0 — 2 ↔ 2 0 — 2 ↔ H B 0 — 2 ↔ Z ↔ I NEG NEG.
Appendix 3. Logic Instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
Appendix 4. Shift Instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
Appendix 5.
Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd BST BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
Appendix 6. Branching Instructions Bcc No.
Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — No.
Appendix 7.
Appendix 8. Block Transfer Instructions EEPMOV No. of States*1 H N Z V C Normal — @@aa @(d, PC) I EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV.
REJ09B0309-0200 Rev. 2.00 Jul. 04, 2007 Page 618 of 692 XOR SUBX OR XOR AND MOV B C D E F BILD CMP BIAND BIST BLD BST TRAPA BEQ A BIXOR BAND AND RTE BNE MOV.B Table A-2 (2) LDC 7 ADDX BIOR BXOR OR BOR BSR BCS RTS BCC AND.B ANDC 6 9 BTST DIVXU BLS XOR.B XORC 5 ADD BCLR MULXU BHI OR.
MOV 7A BRA 58 MOV DAS 1F 79 SUBS 1B 1 CMP CMP ADD BHI 2 ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 SUB SUB BLS OR OR XOR XOR BCS AND AND BEQ BVC SUB 9 BVS NEG NOT DEC ROTR ROTXR DEC ROTL ADDS SLEEP 8 ROTXL EXTU INC 7 SHAR BNE 6 SHLR EXTU INC 5 SHAL BCC LDC/STC 4 SHLL 3 1st byte 2nd byte AH AL BH BL BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table
REJ09B0309-0200 Rev. 2.00 Jul. 04, 2007 Page 620 of 692 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM — Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 25.1, Register Addresses (Address Order). Rev. 2.00 Jul.
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Fetch I ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 Branch Stack Addr. Read Operation J K Byte Data Access L ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.
Appendix Instruction Mnemonic Bcc BCLR BIAND BILD Instruction Fetch I Branch Stack Addr.
Appendix Instruction Mnemonic Instruction Fetch I BIOR BIOR #xx:3, Rd 1 BIOR #xx:3, @ERd 2 1 1 BIST BIXOR BLD BNOT BOR BSET Branch Stack Addr.
Appendix Instruction Mnemonic Instruction Fetch I BTST BTST #xx:3, Rd 1 BTST #xx:3, @ERd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 BXOR CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.L ERs, ERd 1 DAA DAA Rd 1 DAS DAS Rd 1 DEC DEC.B Rd 1 DEC.W #1/2, Rd 1 DEC.
Appendix Instruction Mnemonic Instruction Fetch I INC JMP JSR LDC MOV Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M INC.B Rd 1 INC.W #1/2, Rd 1 INC.L #1/2, ERd 1 JMP @ERn 2 JMP @aa:24 2 JMP @@aa:8 2 JSR @ERn 2 JSR @aa:24 2 JSR @@aa:8 2 LDC #xx:8, CCR 1 LDC Rs, CCR 1 LDC@ERs, CCR 2 1 LDC@(d:16, ERs), CCR 3 1 LDC@(d:24,ERs), CCR 5 1 LDC@ERs+, CCR 2 1 LDC@aa:16, CCR 3 1 LDC@aa:24, CCR 4 1 MOV.B #xx:8, Rd 1 MOV.B Rs, Rd 1 MOV.
Appendix Instruction Mnemonic Instruction Fetch I MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.L ERs, ERd 1 MOV.
Appendix Instruction Mnemonic Instruction Fetch I MULXS MULXS.B Rs, Rd 2 12 MULXS.W Rs, ERd 2 20 MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 MULXU NEG Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N NOP NOP 1 NOT NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.L ERs, ERd 2 ORC ORC #xx:8, CCR 1 POP POP.
Appendix Instruction Mnemonic Instruction Fetch I ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL.B Rd 1 SHAL.W Rd 1 SHAR SHLL SHLR SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.
Appendix Instruction Mnemonic Instruction Fetch I SUBX SUBX #xx:8, Rd 1 SUBX. Rs, Rd 1 XOR XORC XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1 times respectively. 2. It cannot be used in this LSI. Rev. 2.00 Jul.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Logical operations BWL BWL WL BWL @@aa:8 — — — — — — — — — — WL — BWL BWL — @(d:16.PC) — — @aa:24 — — B @aa:16 — — @aa:8 @ERn+/@ERn @(d:24.ERn) @ERn BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — @(d:8.PC) Data MOV transfer POP, PUSH instructions MOVFPE, MOVTPE Arithmetic ADD, CMP operations SUB Rn Instructions #xx Functions @(d:16.
Appendix B. I/O Ports B.1 I/O Port Block Diagrams SBY (Low at a reset or in standby mode) PUCR1 (PUCR16) VCC Internal data bus VCC PDR1 (P16) P16 VSS PCR1 (PCR16) SCI4 module SCK4 output SCK4 input SCK4 input enable SCK4 output enable PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1 TM Figure B.1 (a) Port 1 Block Diagram (P16) (F-ZTAT Version) Rev. 2.00 Jul.
Appendix SBY VCC PDR1 (P16) PCR1 (PCR16) P16 Internal data bus PUCR1 (PUCR16) VCC VSS PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1 Figure B.
Appendix SBY PUCR1 (PUCR1n) PMR1 (AEVL, AEVH) PDR1 (P1n) P1n PCR1 (PCR1n) VSS Internal data bus VCC VCC AEC module AEVH input (P10) AEVL input (P11) PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 1, 0 Figure B.1 (d) Port 1 Block Diagram (P11, P10) Rev. 2.00 Jul.
Appendix SBY PUCR3 (PUCR37) VCC Internal data bus VCC PDR3 (P37) P37 PCR3 (PCR37) VSS SCI4 module SO4 output SO4 output enable PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 TM Figure B.2 (a) Port 3 Block Diagram (P37) (F-ZTAT Version) SBY VCC PUCR3 (PUCR37) PDR3 (P37) PCR3 (PCR37) P37 VSS PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 Figure B.
Appendix SBY PUCR3 (PUCR36) VCC Internal data bus VCC PDR3 (P36) P36 PCR3 (PCR36) VSS SCI4 module SI4 input SI4 input enable PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 TM Figure B.2 (c) Port 3 Block Diagram (P36) (F-ZTAT Version) SBY VCC VCC PUCR3 (PUCR36) Internal data bus PDR3 (P36) PCR3 (PCR36) P36 VSS PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 Figure B.
Appendix SBY PFCR (SC32S) SPCR (SPC32) SCI3_2 module VCC PDR3 (P32) P32 Internal data bus TXD32 output SPCR (SCINV3) PCR3 (PCR32) VSS IIC bus 2 module IIC2 input/output enable SCL output SCL input VSS PDR3: Port data register 3 PCR3: Port control register 3 SPCR: Serial port control register PFCR : Port function control register Figure B.2 (e) Port 3 Block Diagram (P32) Rev. 2.00 Jul.
Appendix SBY SCI3_2 module VCC PFCR (SC32S) PCR3 (PCR31) VSS Internal data bus PDR3 (P31) P31 RXD32 input enable RXD32 input SPCR (SCINV2) VSS I2C bus 2 module IIC input/output enable SDA output SDA input PDR3: Port data register 3 PCR3: Port control register 3 SPCR: Serial port control register PFCR : Port function control register Figure B.2 (f) Port 3 Block Diagram (P31) Rev. 2.00 Jul.
Appendix SBY PUCR (PUCR30) VCC VCC PMR3 (TMOW) RTC module PDR3 (P30) VSS PCR3 (PCR30) Internal data bus TMOW output P30 PFCR (SC32S) SCI3_2 module SCK32 input enable SCK32 output enable SCK32 output SCK32 input PFCR (CLKOUT1) PFCR (CLKOUT0) PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 CLKOUT output φOSC, φOSC/2, φOSC/4 PUCR3: Port pull-up control register 3 PFCR : Port function control register Figure B.2 (g) Port 3 Block Diagram (P30) Rev. 2.
Appendix Timer F module SBY TMOFH output PFCR (SC31S) SPCR (SCINV1) VCC SPCR (SPC31) SCI3_1 module PDR4 (P42) P42 PCR4 (PCR42) Internal data bus TXD31/IrTXD output VSS PMR4 (TMOFH) PDR4: Port data register 4 PCR4: Port contol register 4 PMR4: Port mode register 4 SPCR: Serial port control register PFCR: Port function control register Figure B.3 (a) Port 4 Block Diagram (P42) Rev. 2.00 Jul.
Appendix SBY PFCR (SC31S) SCI3_1 module RXD31/IrRXD input enable VCC PMR4 (TMOFL) RXD31/IrRXD input PCR4 (PCR41) VSS Internal data bus PDR4 (P41) P41 Timer F module TMOFL output PDR4: Port data register 4 PCR4: Port contol register 4 PMR4: Port mode register 4 SPCR: Serial port control register PFCR: Port function control register SPCR (SCINV0) Figure B.3 (b) Port 4 Block Diagram (P41) Rev. 2.00 Jul.
Appendix SBY PFCR (SC31S) SCI3_1 module VCC SCK31 input enable SCK31 output enable SCK31 output P40 PCR4 (PCR40) VSS Internal data bus SCK31 input PDR4 (P40) PMR4 (TMIF) Timer F nodule TMIF input PDR4: Port data register 4 PCR4: Port control register 4 PMR4: Port mode register 4 PFCR: Port function control register Figure B.3 (c) Port 4 Block Diagram (P40) Rev. 2.00 Jul.
Appendix SBY PUCR5 (PUCR5n) VCC VCC PDR5 (P5n) P5n PCR5 (PCR5n) VSS Internal data bus PMR5 (WKPn) WKPn input PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Figure B.4 Port 5 Block Diagram Rev. 2.00 Jul.
Appendix SBY VCC PDR6 (P6n) VCC PCR6 (PCR6n) P6n Internal data bus PUCR6 (PUCR6n) VSS PDR6: Port data register 6 PCR6: Port control register6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure B.5 Port 6 Block Diagram VCC PDR7 (P7n) PCR7 (PCR7n) P7n Internal data bus SBY VSS PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure B.6 Port 7 Block Diagram Rev. 2.00 Jul.
Appendix SBY VCC Internal data bus PDR8 (P8n) PCR8 (PCR8n) P8n VSS PDR8: Port data register 8 PCR8: Port control register 8 n = 7 to 0 Figure B.7 Port 8 Block Diagram PWM module PWM4 output SBY VCC PDR9 (P93) PCR9 (PCR93) P93 VSS PDR9: Port data register 9 PCR9: Port contol register 9 PFCR: Port function control register Figure B.8 (a) Port 9 Block Diagram (P93) Rev. 2.00 Jul.
Appendix PWM module PWM3 output SBY PFCR (PWM3) VCC PDR9 (P92) P92 PCR9 (PCR92) VSS Internal data bus PMR9 (IRQ4) IRQ4 input PDR9: Port data register 9 PCR9: Port contol register 9 PMR9: Port mode register 9 PFCR: Port function control register Figure B.8 (b) Port 9 Block Diagram (P92) Rev. 2.00 Jul.
Appendix PWM module SBY PWMn+1 output VCC Internal data bus PMR9 (PWMn+1) PDR9 (P9n) P9n PCR9 (PCR9n) VSS PDR9: Port data register 9 PCR9: Port contol register 9 PMR9: Port mode register 9 n = 1, 0 Figure B.8 (c) Port 9 Block Diagram (P91, P90) SBY VCC PCRA (PCRAn) PAn VSS PDRA: Port data register A PCRA: Port contol register A n = 3 to 0 Figure B.9 Port A Block Diagram Rev. 2.00 Jul.
Internal data bus Appendix PBn A/D module DEC AMR3 to AMR0 VIN n = 7 to 3 Figure B.10 (a) Port B Block Diagram (PB7 to PB3) Rev. 2.00 Jul.
Appendix PMRB (IRQm) PBn Internal data bus IRQm input A/D module DEC AMR3 to AMR0 VIN PMRB: Port mode register B n = 2 to 0 m = 3, 1, 0 Figure B.10 (b) Port B Block Diagram (PB2 to PB0) Rev. 2.00 Jul.
Appendix SBY PCn PDRC (PCn) VSS PCRC (PCRCn) PDRC: Internal data bus VCC Port data register C PCRC: Port contol register C n = 7 to 0 Figure B.11 Port C Block Diagram (PC7 to PC0) SBY PMRB (IRQ0) VCC PMRE (TMIC) PE7 PDRE (PE7) VSS Internal data bus PMRE (IRQ0) PCRE (PCRE7) Timer C module TMIC input PDRE: PCRE: PMRE: PMRB: Port data register E Port contol register E Port mode register E Port mode register B IRQ0 input Figure B.12 (a) Port E Block Diagram (PE7) Rev. 2.00 Jul.
Appendix SBY VCC Internal data bus PMRE (UD) PE6 PDRE (PE6) VSS PCRE (PCRE6) Timer C module PDRE: Port data register E PCRC: Port contol register E PMRE: Port mode register E UD input Figure B.12 (b) Port E Block Diagram (PE6) SBY VCC PFCR (SC32S) PDRE (PE5) VSS PCRE (PCRE5) PDRE: Port data register E PCRE: Port contol register E SPCR: Serial port control register PFCR: Port function control register SPCR (SCINV3) Figure B.12 (c) Port E Block Diagram (PE5) Rev. 2.00 Jul.
Appendix SBY VCC PDRE (PE4) VSS PCRE (PCRE4) PDRE: PCRE: SPCR: PFCR: Port data register E Port contol register E Serial port control register Port function control register SPCR (SCINV2) Internal data bus PFCR (SC32S) PE4 SCI3_2 module RXD32 input enable RXD32 input Figure B.12 (d) Port E Block Diagram (PE4) Rev. 2.00 Jul.
Appendix SBY VCC PMRB (IRQ1) PDRE (PE3) VSS PCRE (PCRE3) PFCR (SC32S) Internal data bus PMRE (IRQ1) PE3 SCI3_2 module SCK32 input enable SCK32 output enable SCK32 output PDRE: PCRE: PMRE: PMRB: PFCR: Port data register E Port contol register E Port mode register E Port mode register B Port function control register Figure B.12 (e) Port E Block Diagram (PE3) Rev. 2.00 Jul.
Appendix SBY VCC PDRE (PE2) VSS PCRE (PCRE2) PDRE: Port data register E PCRE: Port contol register E Internal data bus SPCR2 (SPC33) PE2 SPCR2 (SCINV5) SCI3_3 module TXD33 output SPCR2: Serial port control register 2 Figure B.12 (f) Port E Block Diagram (PE2) SBY VCC PDRE (PE1) VSS PCRE (PCRE1) SPCR2 (SCINV4) PDRE: Port data register E PCRE: Port contol register E Internal data bus PE1 SCI3_3 module RXD33 input enable RXD33 input SPCR2: Serial port control register 2 Figure B.
Appendix SBY VCC PMRE (IRQ3) PE0 PDRE (PE0) VSS PCRE (PCRE0) Internal data bus PMRB (IRQ3) SCI3_3 module SCK33 input enable SCK33 output enable SCK33 output PDRE: PCRE: PMRE: PMRB: Port data register E Port contol register E Port mode register E Port mode register B Figure B.12 (h) Port E Block Diagram (PE0) Rev. 2.00 Jul.
Appendix SBY VCC PFCR (SC31S) PDRF (PF3) VSS PCRF (PCRF3) SPCR (SCINV1) PDRF: Port data register F PCRF: Port contol register F SPCR: Serial port control register PFCR: Port function control register Internal data bus SPCR (SPC31) PF3 SCI3_1 module TXD31/IrTXD output Figure B.13 (a) Port F Block Diagram (PF3) Rev. 2.00 Jul.
Appendix SBY VCC PDRF (PF2) VSS PCRF (PCRF2) SPCR (SCINV0) PDRF: PCRF: SPCR: PFCR: Port data register F Port contol register F Serial port control register Port function control register Figure B.13 (b) Port F Block Diagram (PF2) Rev. 2.00 Jul.
Appendix SBY VCC PMR9 (IRQ4) PDRF (PF1) VSS PCRF (PCRF1) PFCR (SC31S) PDRF: PCRF: PMRF: PMR9: PFCR: Internal data bus PMRF (IRQ4) PF1 SCI3_1 module SCK31 input enable SCK31 output enable SCK31 output Port data register F Port contol register F Port mode register F Port mode register 9 Port function control register SCK31 input IRQ4 input Figure B.13 (c) Port F Block Diagram (PF1) Rev. 2.00 Jul.
Appendix SBY VCC PF0 PDRF (PF0) VSS PCRF (PCRF0) Internal data bus PMRF (TMIG) Timer G module PDRF: PCRF: PMRF: Port data register F Port contol register F Port mode register F Figure B.13 (d) Port F Block Diagram (PF0) Rev. 2.00 Jul.
Appendix B.
Appendix Operating Mode Reset Active Sleep (High-Speed/ (High-Speed/ Medium-Speed) Medium-Speed) Watch Subactive Subsleep Standby PB7 to PB0 High High impedance impedance*3 High impedance*3 High High High High impedance impedance impedance impedance *3 *3 *1 PC7 to PC0 High Functioning impedance Retained Retained Functioning Retained High impedance *1 PE7 to PE0 High Functioning impedance Retained Retained Functioning Retained High impedance *1 PF3 to PF0 High Functioning impedance Retai
Appendix C. Product Part No. Lineup Product Part No.
100 76 ZD 1 75 e Index mark *1 D y HD *3 bp 25 51 x 26 50 Previous Code 100P6Q-A / FP-100U / FP-100UV F ZE Rev. 2.00 Jul. 04, 2007 Page 664 of 692 E *2 RENESAS Code PLQP0100KB-A A HE REJ09B0309-0200 c1 Detail F Terminal cross section b1 bp MASS[Typ.] 0.6g A2 c L1 L e x y ZD ZE L L1 D E A2 HD HE A A1 bp b1 c c1 Reference Symbol Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.
Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Details) Section 1 Overview 2 The description on the package, LGA-113, is deleted. 1.1 Features • Compact package Figure 1.2 Pin Assignment of 4 H8/38099 Group (PLQP0100KBA) Modified Figure 1.3 Pin Assignment of H8/38099 Group (PTLG0113JAA) Deleted Table 1.1 PTLG0113JA-A Pin Correspondence Deleted Table 1.1 Pin Functions 5 to 10 The column on the PTLG0113JA-A is deleted.
Item Page Revisions (See Manual for Details) Table 4.4 Interrupt Response Times (States) 81 Modified No. Execution Status Number of States 1 1 or 2*1 Interrupt mask level determination Total 18 to 41 Notes: 1. One state in case of an internal interrupt (2 states in case of an external interrupt). 2. Prefetch after interrupt acceptance and interrupt handling routine prefetch. 3. Internal processing after interrupt acceptance and internal processing after vector fetch.
Item Page Revisions (See Manual for Details) 5.3.3 How to Input the External Clock 93 The title of the section modified 5.4.1 Prescaler S 94 Deleted … The output from prescaler S is shared by the on-chip peripheral modules. The division ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode and sleep mode (medium-speed), … 5.5.1 Note on Resonators and Resonator Circuits 95 Modified 5.5.
Item Page Revisions (See Manual for Details) Section 6 Power-Down Modes 102, 6.1.1 System Control Register 1 103 (SYSCR1) 6.1.3 System Control Register 3 105 (SYSCR3) Modified Bit Bit Name Description 6 5 4 STS2 STS1 STS0 Standby Timer Select 2 to 0 1 MA1 Active Mode Clock Select 1 and 0 0 MA0 Select the operating clock frequency in active (medium-speed) mode and sleep (mediumspeed) mode. The MA1 and MA0 bits should be written to in active (high-speed) mode or subactive mode.
Item Page Revisions (See Manual for Details) 6.1.4 Clock Halt Registers 1 to 3 107 (CKSTPR1 to CKSTPR3) Added • CKSTPR1 Bit Bit Name Description 1 FROMCK Flash Memory Module Standby STP*1*3 Flash memory enters standby mode when this bit is cleared to 0. When the addresses H'000000 to H'0000FF of the flash memory space is accessed while this bit is set to 0, the RAM emulation function is enabled and the addresses H'FFFC00 to H'FFFCFF of the RAM space can be accessed. For details, see section 7.
Item Page Revisions (See Manual for Details) Figure 6.1 Mode Transition Diagram 111 Table 6.3 Internal State in Each Operating Mode 115 Modified Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure to enable the interrupt request.
Item Page Revisions (See Manual for Details) 6.2.2 Standby Mode 116 Modified … or the requested interrupt is disabled by the interrupt enable bit. When a reset source is generated in standby mode, the system clock oscillator and the on-chip oscillator for the system clock start. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high. 6.2.
Item Page Revisions (See Manual for Details) 6.2.6 Active (Medium-Speed) Mode 118 The description in this section is modified. 6.3 Direct Transition 119 The description in this section is modified. 6.3.
Item Page Revisions (See Manual for Details) 6.3.3 Direct Transition from 120 Active (Medium-Speed) Mode to Active (High-Speed) Mode Added When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode.
Item Page Revisions (See Manual for Details) 6.3.
Item Page Revisions (See Manual for Details) 6.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode 122 Added When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed.
Item Page Revisions (See Manual for Details) Section 9 I/O Ports 165 SCR3_2 9.2.
Item Page Revisions (See Manual for Details) • 173 P53/WKP3/SEG4 to P50/WKP0/SEG1 pins Modified PCR5 Pin Function PCR5m 9.8.4 Pin Functions • 185 P92/PWM3/IRQ4 pin 0 P5m input pin 1 P5m output pin 0 WKPm input pin 1 Setting prohibited x SEGm+1 output pin PCR9 Pin Function Modified PCR92 0 9.10.
Item Page Revisions (See Manual for Details) • 193 PB0/AN0/IRQ0 pin Modified AMR Pin Function CH3 to CH0 Other than B'0100 9.12.
Item Page Revisions (See Manual for Details) 9.13.4 Pin Functions 205 • Modified SCR3_1 PF1 (/SCK31/IRQ4) pin PCRF CKE0 x x x x x 0 PF1 input pin 1 PF1 output pin 0 0 1 1 0 1 9.16.
Item Page Revisions (See Manual for Details) Section 10 Realtime Clock (RTC) 220 Modified RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than φw/4 is selected, the RTC is disabled and operates as an 8-bit free running counter. 10.3.
Item Page Revisions (See Manual for Details) 11.3.1 Timer Mode Register C (TMC) 229 Modified Bit Bit Name Description 6 TMC6 Counter Up/Down Control 5 TMC5 Specifies whether TCC functions as an upcounter or down-counter, or whether selection of counting up or down is controlled by the input signal level on the UD pin. 00: TCC is an up-counter 01: TCC is a down-counter 1x: Selection through the signal level on the UD pin UD pin input high: Down-counter UD pin input low: Up-counter 11.4.
Item Page Revisions (See Manual for Details) Figure 12.4 TMOFH/TMOFL Output Timing 245 Modified Figure 12.5 TCF Clear Timing 245 Added Figure 12.6 Compare Match Flag Set Timing 246 Added 12.6.1 16-Bit Timer Mode 248 Modified … However, if the written data and the counter value match, there is a probability of a compare match signal being generated and not being generated. 12.6.
Item Page Revisions (See Manual for Details) Section 14 16-Bit Timer Pulse Unit (TPU) 285 Deleted TCNT is a 16-bit readable/writable counter. The TPU has a total of two TCNT counters, one for each channel. 14.3.6 Timer Counter (TCNT) TCNT is initialized to H'0000 by a reset or in hardware standby mode. Figure 14.2 16-Bit Register Access Operation [CPU ↔ TCNT (16 Bits)] 288 Modified Module data bus Upper 8 bits Lower 8 bits TCNT Figure 14.20 Example of PWM Mode Operation (3) 304 14.
Item Page Revisions (See Manual for Details) Section 16 Watchdog Timer 338 16.2.1 Timer Control/Status Register WD1 (TCSRWD1) Added Bit Bit Name Description 0 WRST Watchdog Timer Reset Indicates whether a reset caused by the watchdog timer is generated. This bit is not cleared by a reset caused by the watchdog timer. [Setting condition] When TCWD overflows and an internal reset signal is generated Section 17 Serial Communication Interface 3 (SCI3, IrDA) 377 Added Bit Bit Name Description 3 17.3.
Item Page Revisions (See Manual for Details) Section 20 A/D Converter 444 20.3.1 A/D Result Register (ADRR) 20.7.3 Usage Notes Modified ADRR is a 16-bit read-only register that stores the results of A/D conversion. The data is stored in the upper 10 bits of ADRR. ADRR can be read by the CPU at any time, … 454 Deleted : 3. When A/D conversion is started after clearing module standby mode, wait for 10φ clock cycles before starting A/D conversion. 4.
Item Page Revisions (See Manual for Details) 21.4.3 3-V Constant-Voltage Power Supply Circuit 473 Modified … Before activating a step-up circuit, operate the LCD controller/driver, and set the duty cycle, pin function, display data, frame frequencies, etc. Insert a capacitance of 0.1 µF between the C1 pin and C2 pin, and connect a capacitance of 0.1 µF to each of V1, V2, and V3 pins. 474 Modified Notes: : 4.
Item Page Revisions (See Manual for Details) Section 26 Electrical Characteristics 554 to Modified 561 Table 26.2 DC Characteristics Table 26.3 Control Signal Timing 562 to Modified 566 Table 26. 6 A/D Converter Characteristics 569 Modified 595 Notes: Table 26.16 A/D Converter Characteristics : 3. AISTOP2 is the current at a reset, in standby or watch mode while the A/D converter is idle, or in the module standby state. Table 26.7 LCD Characteristics 570 Modified Table 26.
Rev. 2.00 Jul.
Index Numerics D 16-bit timer mode ................................... 242 16-bit timer pulse unit............................. 271 8-bit timer mode ..................................... 243 Data reading procedure ........................... 223 Data transfer instructions .......................... 22 A A/D converter ......................................... 441 Absolute address....................................... 33 Acknowledge .......................................... 496 Address break ...........
Interrupt mask bit (I)................................. 16 IrDA........................................................ 401 L Large current ports...................................... 2 LCD controller/driver ............................. 455 LCD display............................................ 466 LCD RAM .............................................. 468 Logic operations instructions.................... 25 Power-on reset circuit ............................. 517 Prescaler W ...........................
ECH ............................ 327, 529, 536, 542 ECL............................. 327, 529, 536, 542 ECPWCR.................... 321, 528, 535, 542 ECPWDR.................... 322, 528, 536, 542 FENR .......................... 133, 526, 533, 540 FLMCR1..................... 129, 526, 533, 540 FLMCR2..................... 130, 526, 533, 540 FLPWCR .................... 132, 526, 533, 540 ICCR1......................... 482, 527, 534, 541 ICCR2......................... 485, 527, 534, 541 ICDRR ..................
RWKDR ......................216, 527, 534, 541 SAR .............................494, 528, 535, 541 SCR3............................356, 529, 536, 542 SCR4............................415, 526, 533, 540 SCSR4 .........................418, 526, 533, 540 SMR.............................353, 529, 536, 542 SPCR ...........................373, 529, 536, 542 SSR ..............................358, 529, 536, 543 SUB32CR ......................86, 527, 534, 541 SYSCR1 ......................102, 531, 538, 545 SYSCR2 ...
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/38099 Group Publication Date: Rev.1.00, Mar. 28, 2006 Rev.2.00, Jul. 04, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8/38099Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0309-0200
