Datasheet

Section 4 Interrupt Controller
Rev. 2.00 Jul. 04, 2007 Page 59 of 692
REJ09B0309-0200
Section 4 Interrupt Controller
4.1 Features
This LSI includes an interrupt controller, which has the following features.
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Three mask
levels can be set for each module for all interrupts except an NMI and address break.
• Interrupts can be enabled or disabled in three levels by the INTM1 and INTM0 bits in the
interrupt mask register (INTM).
• Fourteen external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising or falling edge
sensing can be selected for NMI. Rising or falling edge sensing can be selected for IRQ0,
IRQ1, IRQ3, IRQ4, and WKP0 to WKP7. Rising, falling, or both edge sensing can be selected
for IRQAEC.
A block diagram of the interrupt controller is shown in figure 4.1.
IENR1
IPR
I
CCR
Priority
determination
NMI/IRQ/
WKP input
IENR1:
IPR:
CCR:
INTM:
IRQ enable register 1
Interrupt priority register
Condition code register
Interrupt mask register
Internal interrupt source
TPU, SCI, etc.
[Legend]
Interrupt request
Vector number
............
INTM
External interrupt
input
Figure 4.1 Block Diagram of Interrupt Controller