Datasheet

Section 4 Interrupt Controller
Rev. 2.00 Jul. 04, 2007 Page 66 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
0 IRRI0 0 R/W IRQ0 Interrupt Request Flag
[Setting condition]
The IRQ0 pin is set as the interrupt input pin and the
specified edge is detected
[Clearing condition]
Writing of 0 to this bit
4.3.6 Interrupt Request Register 2 (IRR2)
IRR2 indicates the state of the direct transition, A/D converter, timer G, timer F, timer C, and
asynchronous event counter interrupt requests.
Bit Bit Name
Initial
Value
R/W Description
7 IRRDT 0 R/W Direct Transition Interrupt Request Flag
[Setting condition]
Execution of a SLEEP instruction while the DTON bit in
SYSCR2 is set to 1, so that a direct transition is made
to sleep mode
[Clearing condition]
Writing of 0 to this bit
6 IRRAD 0 R/W A/D Converter Interrupt Request Flag
[Setting condition]
When A/D conversion ends
[Clearing condition]
Writing of 0 to this bit
5 — 0 — Reserved
This bit is always read as 0 and cannot be modified.
4 IRRTG 0 R/W Timer G Interrupt Request Flag
[Setting condition]
The timer G input capture or overflow occurs.
[Clearing condition]
Writing of 0 to this bit