Datasheet

Section 4 Interrupt Controller
Rev. 2.00 Jul. 04, 2007 Page 71 of 692
REJ09B0309-0200
4.3.9 Interrupt Mask Register (INTM)
INTM is an 8-bit readable/writable register that controls 3-level interrupt masking depending on
the combination of the INTM0 and INTM1 bits.
Bit Bit Name
Initial
Value
R/W Description
7 to 2  All 1  Reserved
These bits are always read as 1 and cannot be
modified.
1
0
INTM1
INTM0
0
0
R/W
R/W
Set the interrupt mask level.
1x: Mask an interrupt with mask level 1 or less
01: Mask an interrupt with mask level 0
00: Accept all interrupts
[Legend]
x: Don't care
4.4 Interrupt Sources
4.4.1 External Interrupts
There are 14 external interrupts: NMI, WKP7 to WKP0, IRQ4, IRQ3, IRQAEC, IRQ1, and IRQ0.
(1) NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the state of
the I bit in CCR. The NMIEG bit in IEGR can be used to select whether an interrupt is requested
at a rising edge or a falling edge on the NMI pin.
(2) WKP7 to WKP0 Interrupts
WKP7 to WKP0 interrupts are requested by the rising or falling edge input signals at the WKP7 to
WKP0 pins.
When the rising or falling edge is input while the WKP7 to WKP0 pin functions are selected by
PMR5, the corresponding bit in IWPR is set to 1 and an interrupt request is generated.
Clearing the IENWP bit in IENR1 to 0 disables the wakeup interrupt request to be accepted.
Setting the I bit in CCR to 1 masks all interrupts.