Datasheet

Section 4 Interrupt Controller
Rev. 2.00 Jul. 04, 2007 Page 77 of 692
REJ09B0309-0200
4.6 Operation
NMI and address break interrupts are accepted at all times except in the reset state. In the case of
IRQ interrupts, WKP interrupts, and on-chip peripheral module interrupts, an enable bit is
provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt
request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt
controller.
Table 4.3 shows the interrupt control states. Figure 4.2 shows a flowchart of the interrupt
acceptance operation.
Four-level interrupt masking is controlled according to the combination of the I bit in CCR and the
INTM1 and INTM0 bits in INTM.
Table 4.3 Interrupt Control States
CCR INTM
I INTM1 INTM0 States
1 x x All interrupts other than NMI and address break are masked.
1 x Interrupts with mask level 1 or less are masked.
0 1 Interrupts with mask level 0 are masked.
0
0 0 All interrupts are accepted.
[Legend]
x: Don't care
1. If an interrupt source whose enable bit is set to 1 occurs, an interrupt request is sent to the
interrupt controller.
2. With referring to the INTM1 and INTM0 bits in INTM and the I bit in CCR, control the
following.
 The interrupt request is held pending when the I bit is set to 1.
 When the I bit is cleared to 0 and INTM1 bit is set to 1, interrupts with mask level 1 or less
are held pending.
 When the I bit is cleared to 0, INTM1 bit is cleared to 0, and INTM0 bit is set to 1,
interrupt requests with mask level 0 are held pending.
 When the I bit, INTM1 bit, and INTM0 bit are all cleared to 0, all interrupt requests are
accepted.