Datasheet

Rev. 2.00 Jul. 04, 2007 Page x of xl
3.4 Stack Status after Exception Handling................................................................................. 52
3.5 Usage Notes ......................................................................................................................... 53
3.5.1 Notes on Stack Area Use ........................................................................................ 53
3.5.2 Notes on Rewriting Port Mode Registers ............................................................... 54
3.5.3 Method for Clearing Interrupt Request Flags ......................................................... 57
Section 4 Interrupt Controller..............................................................................59
4.1 Features................................................................................................................................ 59
4.2 Input/Output Pins................................................................................................................. 60
4.3 Register Descriptions ...........................................................................................................60
4.3.1 Interrupt Edge Select Register (IEGR) ................................................................... 61
4.3.2 Wakeup Edge Select Register (WEGR).................................................................. 62
4.3.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 63
4.3.4 Interrupt Enable Register 2 (IENR2) ...................................................................... 64
4.3.5 Interrupt Request Register 1 (IRR1) ....................................................................... 65
4.3.6 Interrupt Request Register 2 (IRR2) ....................................................................... 66
4.3.7 Wakeup Interrupt Request Register (IWPR) .......................................................... 68
4.3.8 Interrupt Priority Registers A to F (IPRA to IPRF) ................................................ 70
4.3.9 Interrupt Mask Register (INTM) ............................................................................ 71
4.4 Interrupt Sources.................................................................................................................. 71
4.4.1 External Interrupts .................................................................................................. 71
4.4.2 Internal Interrupts ................................................................................................... 73
4.5 Interrupt Exception Handling Vector Table......................................................................... 73
4.6 Operation ............................................................................................................................. 77
4.6.1 Interrupt Exception Handling Sequence ................................................................. 79
4.6.2 Interrupt Response Times ....................................................................................... 81
4.7 Usage Notes ......................................................................................................................... 82
4.7.1 Contention between Interrupt Generation and Disabling........................................ 82
4.7.2 Instructions that Disable Interrupts......................................................................... 83
4.7.3 Interrupts during Execution of EEPMOV Instruction............................................. 83
4.7.4 IENR Clearing ........................................................................................................ 83
Section 5 Clock Pulse Generator.........................................................................85
5.1 Register Description............................................................................................................. 86
5.1.1 SUB32k Control Register (SUB32CR)................................................................... 86
5.1.2 Oscillator Control Register (OSCCR) .................................................................... 87
5.2 System Clock Generator ...................................................................................................... 88
5.2.1 Connecting Crystal Resonator ................................................................................ 88
5.2.2 Connecting Ceramic Resonator .............................................................................. 89
5.2.3 External Clock Input Method.................................................................................. 89