Datasheet

Section 4 Interrupt Controller
Rev. 2.00 Jul. 04, 2007 Page 82 of 692
REJ09B0309-0200
4.7 Usage Notes
4.7.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction
such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the
interrupt concerned will still be enabled on completion of the instruction, and so interrupt
exception handling for that interrupt will be executed on completion of the instruction. However,
if there is an interrupt request with a higher mask level than that interrupt, interrupt exception
handling will be executed for the interrupt with a higher mask level, and the interrupt with a lower
mask level will be ignored. The same also applies when an interrupt source flag is cleared to 0.
Figure 4.4 shows an example in which the TGIEA bit in TIER of the 16-bit timer pulse unit (TPU)
is cleared to 0.
TIER address
φ
TIER write cycle by CPU TGIA exception handling
Internal address
bus
Internal write
signal
TGIEA
TGIA
TGIA interrupt
signal
Figure 4.4 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.