Datasheet

Section 5 Clock Pulse Generator
Rev. 2.00 Jul. 04, 2007 Page 85 of 692
REJ09B0309-0200
Section 5 Clock Pulse Generator
The clock pulse generator incorporated into this LSI consists of a system clock pulse generator
circuit that consists of a system clock oscillator, system clock divider, and an on-chip oscillator for
the system clock, and a subclock pulse generator circuit that consists of a subclock oscillator and
subclock divider.
Figure 5.1 is a block diagram of the clock pulse generator.
System
clock
oscillator
On-chip
oscillator for
system clock
Subclock
oscillator
Subclock
divider
System
clock
divider
Prescaler S
(17 bits)
OSC1
R
OSC
IRQAEC
OSC2
X1
X2
System clock pulse generator circuit
Subclock pulse generator circuit
φ
OSC
(f
OSC
)
φ
OSC
(f
OSC
)
φ
W
(f
W
)
φ
W
/2
φ
W
/4
φ
SUB
φ/2
φ
W
/4
φ
W
/2
φ/131072
φ
W
/8
φ
φ
OSC
/8
φ
OSC
φ
OSC
/16
φ
OSC
/32
φ
OSC
/64
Prescaler W
(8 bits)
φ
W
/8
φ
W
/1024
φ
W
to
to
*
Note: * The system clock can be output from the on-chip oscillator for the system clock or system clock oscillator by the
input level of the IRQAEC pin during an internal reset except for the one by the watchdog timer.
Figure 5.1 Block Diagram of Clock Pulse Generator
The basic clock signals that drive the CPU and on-chip peripheral modules are the system clock
(φ) and subclock (φ
SUB
). Prescaler S frequency-divides the clock signal S to produce clock signals
at rates from φ/131072 to φ/2, and prescaler W frequency-divides the watch clock φ
w
/4, which is
the watch clock frequency-divided by four, to produce clock signals from at rates from φ
w
/1024 to
φ
w
/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules.
Since the on-chip oscillator for the system clock is available, the system clock can be selected to
be output from the on-chip oscillator for the system clock or system clock oscillator by the input
level of the IRQAEC pin.