Datasheet

Section 5 Clock Pulse Generator
Rev. 2.00 Jul. 04, 2007 Page 94 of 692
REJ09B0309-0200
5.4 Prescalers
This LSI has two prescalers (prescaler S and prescaler W), and each has its own input clock signal.
Prescaler S is a 17-bit counter that has the system clock (φ) as its input clock. Its prescaled outputs
provide the internal clock signals that drive the on-chip peripheral modules.
Prescaler W is an 8-bit counter that has a frequency-divided signal (φ
W
/4) derived from the watch
clock (φ
W
) as its input clock. Its prescaled outputs provide the internal clock signals that drive the
on-chip peripheral modules.
5.4.1 Prescaler S
Prescaler S is a 17-bit counter using the system clock (φ) as its input clock. A divided output is
used as an internal clock of an on-chip peripheral module. Prescaler S is initialized to H'00000 at a
reset, and starts counting up on exit from the reset state. Prescaler S stops and is initialized to
H'00000 in standby mode, watch mode, subactive mode, and subsleep mode. The CPU cannot
read from or write to prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. In active (medium-
speed) mode and sleep mode (medium-speed), the clock input to prescaler S is determined by the
division ratio designated by the MA1 and MA0 bits in SYSCR2.
5.4.2 Prescaler W
Prescaler W is an 8-bit counter that has a frequency-divided signal (φ
W
/4) derived from the watch
clock (φ
W
) as its input clock. This signal is further divided to produce internal clock signals for the
on-chip peripheral modules. Prescaler W is initialized to H'00 by a reset, and starts counting up on
exit from the reset state. Prescaler W stops in standby mode, but continues to operate in watch
mode, subactive mode, and subsleep mode.