Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Jul. 04, 2007 Page 102 of 692
REJ09B0309-0200
6.1 Register Descriptions
The registers related to power-down modes are as follows.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• System control register 3 (SYSCR3)
• Clock halt registers 1 to 3 (CKSTPR1 to CKSTPR3)
6.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes with SYSCR2 and SYSCR3.
Bit Bit Name
Initial
Value
R/W Description
7 SSBY 0 R/W
Software Standby
Selects the mode to transit after the execution of the
SLEEP instruction.
0: A transition is made to sleep mode or subsleep
mode.
1: A transition is made to standby mode or watch mode.
For details, see table 6.2.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
Specify the time the CPU and peripheral modules wait
for stable clock operation after exiting from standby
mode, subactive mode, or watch mode to active mode
or sleep mode. These bits should be specified together
with the STS3 bit in SYSCR3 according to the operating
frequency so that the wait time is at least equal to the
oscillation stabilization time. The relationship between
the specified value and the number of wait states is
shown in table 6.1.
When an external clock is to be used, the minimum
value (STS3 = 0, STS2 = 1, STS1 = 0, STS0 = 1) is
recommended. When the on-chip oscillator for the
system clock is to be used, four states (STS3 = 1, STS2
= 1, STS1 = 0, STS0 = 1) are recommended. If a
setting other than the recommended value is made,
operation may start before the end of the wait time.