Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Jul. 04, 2007 Page 103 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
3 LSON 0 R/W Selects the system clock (φ) or subclock (φ
SUB
) as the
CPU operating clock when watch mode is cleared.
0: The CPU operates on the system clock (φ)
1: The CPU operates on the subclock (φ
SUB
)
2 TMA3 0 R/W Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY and
LSON in SYSCR1 and bits DTON and MSON in
SYSCR2. For details, see table 6.2.
1
0
MA1
MA0
1
1
R/W
R/W
Active Mode Clock Select 1 and 0
Select the operating clock in active (medium-speed)
mode and sleep (medium-speed) mode. The MA1 and
MA0 bits should be written to in active (high-speed)
mode or subactive mode.
00: φ
OSC
/8
01: φ
OSC
/16
10: φ
OSC
/32
11: φ
OSC
/64