Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Jul. 04, 2007 Page 104 of 692
REJ09B0309-0200
6.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes with SYSCR1 and SYSCR3.
Bit Bit Name
Initial
Value
R/W Description
7 to 5  All 1  Reserved
These bits are always read as 1 and cannot be
modified.
4 NESEL 1 R/W Noise Elimination Sampling Frequency Select
This bit selects the sampling frequency of φ
OSC
when φ
W
is sampled. When a system clock is used, clear this bit
to 0.When the on-chip oscillator is selected, set this bit
to 1.
0: Sampling rate is φ
OSC
/16.
1: Sampling rate is φ
OSC
/4.
3 DTON 0 R/W Direct Transfer on Flag
Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY,
TMA3, and LSON in SYSCR1 and bit MSON in
SYSCR2. For details, see table 6.2.
2 MSON 0 R/W Medium Speed on Flag
After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed)
mode.
0: Operation in active (high-speed) mode
1: Operation in active (medium-speed) mode
1
0
SA1
SA0
0
0
R/W
R/W
Subactive Mode Clock Select 1 and 0
Select the operating clock frequency in subactive and
subsleep modes. The operating clock frequency
changes to the set frequency after the SLEEP
instruction is executed.
00: φ
W
/8
01: φ
W
/4
10: φ
W
/2
11: Setting prohibited