Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Jul. 04, 2007 Page 107 of 692
REJ09B0309-0200
6.1.4 Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3)
CKSTPR1, CKSTPR2, and CKSTPR3 allow the on-chip peripheral modules to enter the standby
state in module units.
• CKSTPR1
Bit Bit Name
Initial
Value
R/W Description
7 S4CKSTP*
1
*
3
1 R/W SCI4 Module Standby
The SCI4 enters standby mode when this bit is cleared to
0.
6 S31CKSTP 1 R/W SCI3_1 Module Standby*
2
The SCI3_1 enters standby mode when this bit is cleared
to 0.
5 S32CKSTP 1 R/W SCI3_2 Module Standby*
2
The SCI3_2 enters standby mode when this bit is cleared
to 0.*
1
4 ADCKSTP 1 R/W A/D Converter Module Standby
The A/D converter enters standby mode when this bit is
cleared to 0.
3 — 1 R/W Reserved
This bit can be read from or written to.
2 TFCKSTP 1 R/W Timer F Module Standby
Timer F enters standby mode when this bit is cleared to 0.
1 FROMCK
STP*
1
*
3
1 R/W Flash Memory Module Standby
Flash memory enters standby mode when this bit is cleared
to 0. When the addresses H'000000 to H'0000FF of the
flash memory space is accessed while this bit is set to 0,
the RAM emulation function is enabled and the addresses
H'FFFC00 to H'FFFCFF of the RAM space can be
accessed. For details, see section 7.4, Using RAM to
Emulate Flash Memory.
The RAM emulation function is supported only by the F-
ZTAT version.
0 RTCCKSTP 1 R/W RTC Module Standby
RTC enters standby mode when this bit is cleared to 0.