Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Jul. 04, 2007 Page 109 of 692
REJ09B0309-0200
• CKSTPR3
Bit Bit Name
Initial
Value
R/W Description
7 S33CKSTP 1 R/W SCI3_3 Module Standby*
2
The SCI3_3 enters standby mode when this bit is cleared
to 0.
6 TCCKSTP 1 R/W Timer C Module Standby
The timer C enters standby mode when this bit is cleared
to 0.
5 TGCKSTP 1 R/W Timer G Module Standby
The timer G enters standby mode when this bit is cleared
to 0.
4 PW4CKSTP 1 R/W PWM4 Module Standby
The PWM4 enters standby mode when this bit is cleared
to 0.
3 PW3CKSTP 1 R/W PWM3 Module Standby
The PWM3 enters standby mode when this bit is cleared
to 0.
2 to 0 — All 0 — Reserved
These bits are always read as 0 and cannot be modified.
Notes: 1. This bit is always read as 1 and cannot be modified in the masked ROM version.
2. When the SCI3 module standby is set, all registers in the SCI3 enter the reset state.
3. This bit must be set to 1 when the on-chip emulator is used.
4. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the
WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0.
However, the watchdog timer does not enter module standby mode and continues
operating. When the WDON bit is cleared to 0 by software, this bit is valid and the
watchdog timer enters module standby mode.