Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Jul. 04, 2007 Page 116 of 692
REJ09B0309-0200
6.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, on-chip oscillator for the
system clock, subclock oscillator, and on-chip peripheral modules continues operating. In sleep
(medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the
MA1 and MA0 bits in SYSCR1. CPU register contents are retained.
Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and
interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the
requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition
is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed)
mode to active (medium-speed) mode.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an
interrupt request signal is synchronous with the system clock, the maximum time of 2/φ (s) may be
delayed from the point at which an interrupt request signal occurs until the interrupt exception
handling is started.
6.2.2 Standby Mode
In standby mode, the system clock oscillator and on-chip oscillator for the system clock is halted,
so the CPU and on-chip peripheral modules except for WDT and asynchronous event counter stop
functioning. However, as long as the rated voltage is supplied, the contents of CPU registers and
some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as
long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the
high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock
oscillator and on-chip oscillator for the system clock start. After the time set in the STS2 to STS0
bits in SYSCR1 and the STS3 bit in SYSCR3 has elapsed, standby mode is cleared and interrupt
exception handling starts. After standby mode is cleared, a transition is made to active (high-
speed) or active (medium-speed) mode according to the MSON bit in SYSCR2. Standby mode is
not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt
enable bit.
When a reset source is generated in standby mode, the system clock oscillator and the on-chip
oscillator for the system clock start. The RES pin must be kept low until the system clock
oscillator output stabilizes and the t
REL
period has elapsed. The CPU starts reset exception handling
when the RES pin is driven high.