Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Jul. 04, 2007 Page 117 of 692
REJ09B0309-0200
6.2.3 Watch Mode
In watch mode, the system clock oscillator, on-chip oscillator for the system clock, and CPU
operation stop and on-chip peripheral modules stop functioning except for the WDT, RTC, timer
C, timer F, timer G, asynchronous event counter, and LCD controller/driver. However, as long as
the rated voltage is supplied, the contents of CPU registers, some on-chip peripheral module
registers, and on-chip RAM are retained. The I/O ports retain their state before the transition.
Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and
interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is
made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on
the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is
made to active mode, after the time set in the STS2 to STS0 bits in SYSCR1 and the STS3 bit in
SYSCR3 has elapsed, interrupt exception handling starts. Watch mode is not cleared if the I bit in
CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register.
When a reset source is generated in watch mode, the system clock oscillator starts. The RES pin
must be kept low until the system clock oscillator output stabilizes and the t
REL
period has elapsed.
The CPU starts reset exception handling when the RES pin is driven high.
6.2.4 Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules other than the TPU,
A/D converter, PWM, IIC2, and address break continue running. As long as a required voltage is
applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip
peripheral modules are retained. I/O ports keep the same states as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to
subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable register.
When a reset source is generated in subsleep mode, the system clock oscillator starts. The RES pin
must be kept low until the system clock oscillator output stabilizes and the t
REL
period has elapsed.
The CPU starts reset exception handling when the RES pin is driven high.