Datasheet

Section 6 Power-Down Modes
Rev. 2.00 Jul. 04, 2007 Page 125 of 692
REJ09B0309-0200
6.5.2 Notes on External Input Signal Changes before/after Standby Mode
(1) When External Input Signal Changes before/after Standby Mode or Watch Mode
When an external input signal such as NMI, IRQ, WKP, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φ
SUB
(referred to together in this section as the internal clock). As the internal clock stops in standby
mode and watch mode, the width of external input signals requires careful attention when a
transition is made via these operating modes. Ensure that external input signals conform to the
conditions stated in (3), Recommended Timing of External Input Signals, below.
(2) When External Input Signals cannot be Captured because Internal Clock Stops
The case of falling edge capture is shown in figure 6.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active mode or subactive mode, after oscillation is started by an
interrupt via a different signal, the external input signal cannot be captured if the high-level width
at that point is less than 2 t
cyc or 2 tsubcyc.
(3) Recommended Timing of External Input Signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of at
least 2 t
cyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as
shown in "Capture possible: case 1."
External input signal capture is also possible with the timing shown in "Capture possible: case 2"
and "Capture possible: case 3," in which a 2 t
yc or 2 tsubcyc level width is secured.