Datasheet

Section 10 Realtime Clock (RTC)
Rev. 2.00 Jul. 04, 2007 Page 220 of 692
REJ09B0309-0200
10.3.7 Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by
the RUN bit in RTCCR1. When a clock other than φ
w
/4 is selected, the RTC is disabled and
operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter,
RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to the
FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock in
which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode. The φ
w
clock
is output in active, sleep, subactive, subsleep, and watch modes.
Bit Bit Name
Initial
Value
R/W Description
7 — —/(0)* R Reserved
This bit cannot be modified.
6
5
4
RCS6
RCS5
SUB32K
0
0
0
R/W
R/W
R/W
Clock Output Selection
Select a clock output from the TMOW pin when setting
the TMOW bit in PMR3 to 1.
000: φ/4
010: φ/8
100: φ/16
110: φ/32
xx1: φ
w
3
2
1
0
RCS3
RCS2
RCS1
RCS0
1
0
0
0
R/W
R/W
R/W
R/W
Clock Source Selection
0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1000 : φ
w
/4⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ RTC operation
1001 to 1111: Setting prohibited
[Legend]
x: Don't care.
Note: * This is the initial value after a reset by the RST bit in RTCCR1.