Datasheet

Section 11 Timer C
Rev. 2.00 Jul. 04, 2007 Page 227 of 692
REJ09B0309-0200
Section 11 Timer C
Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This
timer has two operation modes, interval and auto reload.
11.1 Features
Features of timer C are given below.
• Choice of nine internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φ
W
/4, φ
W
/256,
and φ
W
/1024) or an external clock (can be used to count external events).
• An interrupt is requested when the counter overflows.
• Up/down-counter switching is selected either by the register specification or the external input
level specification.
• Subactive mode or subsleep mode operation is possible when φ
W
/4, φ
W
/256, or φ
W
/1024 is
selected as the internal clock, or when an external clock is selected.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used (for details, see section 6.4, Module Standby Function).
UD
φ
TMIC
φ
w
/4
PSS
TMC
Internal data bus
TCC
TLC
IRRTC
[Legend]
TMC:
TCC:
TLC:
IRRTC:
PSS:
PSW:
Timer mode register C
Timer counter C
Timer load register C
Timer C overflow interrupt request flag
Prescaler S
Prescaler W
PSW
Figure 11.1 Block Diagram of Timer C