Datasheet

Section 11 Timer C
Rev. 2.00 Jul. 04, 2007 Page 233 of 692
REJ09B0309-0200
11.4.2 Auto-Reload Timer Operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a
reload value is set in TLC, the same value is loaded into TCC, becoming the value from which
TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that
value. The overflow/underflow period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in
TCC.
11.4.3 Event Counter Operation
Timer C can operate as an event counter, with the TMIC pin as the event input pin. External event
counting is selected by setting bits TMC3 to TMC0 in the timer mode register C (TMC) to B'0111
or B'1111, and setting the TMIC bit in PMRE to 1. TCC counts up/down at the rising/falling edge
of an external event signal input at the TMIC pin.
The external event input signal is not counted correctly if it does not satisfy the high width or low
width of the input pin.
11.4.4 TCC Up/Down Control by the External Input Pin
With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 in TMC
is set to 1, TCC functions as an up-counter when UD pin input is low, and as a down-counter
when high.
When using UD pin input, set the UD bit in PMRE to 1.