Datasheet

Section 11 Timer C
Rev. 2.00 Jul. 04, 2007 Page 234 of 692
REJ09B0309-0200
11.5 Timer C Operation States
Table 11.2 summarizes the timer C operation states.
Table 11.2 Timer C Operation States
Operation Mode Reset Active Sleep Watch Sub-active Sub-sleep Standby
Module
Standby
TCC Interval Reset Functioning*
1
Functioning*
1
Functioning/
Halted*
2
Functioning/
Halted*
3
Functioning/
Halted*
3
Halted Halted
Auto reload Reset Functioning*
1
Functioning*
1
Functioning/
Halted*
2
Functioning/
Halted*
3
Functioning/
Halted*
3
Halted Halted
TMC Reset Functioning Retained Retained Functioning Retained Retained Retained
Notes: 1. When φ
W
/4, φ
W
/256, or φ
W
/1024 is selected as the TCC internal clock in active mode or
sleep mode, since the system clock and internal clock are mutually asynchronous,
synchronization is maintained by a synchronization circuit. This results in a maximum
count cycle error of 1/φ (s).
2. When the counter is operated in watch mode, select φ
W
/4, φ
W
/256, or φ
W
/1024 as the
clock.
3. When the counter is operated in subactive mode or subsleep mode, either select
φ
W
/4, φ
W
/256, or φ
W
/1024 as the internal clock or select an external clock. The counter
will not operate on any other internal clock. If φ
W
/4 is selected as the internal clock for
the counter when φ
W
/8 has been selected as subclock φ
SUB
, the lower 2 bits of the
counter operate on the same cycle, and the operation of the least significant bit is
unrelated to the operation of the counter.