Datasheet

Rev. 2.00 Jul. 04, 2007 Page xxvi of xl
Figure 5.4 Example of External Clock Input ................................................................................ 89
Figure 5.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator................................ 91
Figure 5.6 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 92
Figure 5.7 Pin Connection when not Using Subclock .................................................................. 92
Figure 5.8 Pin Connection when Inputting External Clock .......................................................... 93
Figure 5.9 Example of Crystal and Ceramic Resonator Arrangement.......................................... 95
Figure 5.10 Negative Resistance Measurement and Circuit Modification Suggestions ............... 96
Figure 5.11 Example of Incorrect Board Design .......................................................................... 97
Figure 5.12 Oscillation Stabilization Wait Time .......................................................................... 98
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ......................................................................................... 111
Figure 6.2 Standby Mode Transition and Pin States................................................................... 124
Figure 6.3 External Input Signal Capture when Signal Changes before/after Standby Mode
or Watch Mode ......................................................................................................... 126
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration.......................................................................... 128
Figure 7.2 Sample Flowchart of Programming/Erasing in User Program Mode........................ 137
Figure 7.3 Address Map of Overlaid RAM Area .......................................................................139
Figure 7.4 Program/Program-Verify Flowchart ......................................................................... 141
Figure 7.5 Erase/Erase-Verify Flowchart ................................................................................... 144
Figure 7.6 Module Standby Mode Setting when RAM Emulation is not Used.......................... 148
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................151
Figure 9.2 Port 3 Pin Configuration............................................................................................160
Figure 9.3 Port 4 Pin Configuration............................................................................................166
Figure 9.4 Port 5 Pin Configuration............................................................................................170
Figure 9.5 Port 6 Pin Configuration............................................................................................174
Figure 9.6 Port 7 Pin Configuration............................................................................................178
Figure 9.7 Port 8 Pin Configuration............................................................................................180
Figure 9.8 Port 9 Pin Configuration............................................................................................183
Figure 9.9 Port A Pin Configuration........................................................................................... 186
Figure 9.10 Port B Pin Configuration......................................................................................... 190
Figure 9.11 Port C Pin Configuration......................................................................................... 194
Figure 9.12 Port E Pin Configuration .........................................................................................196
Figure 9.13 Port F Pin Configuration ......................................................................................... 202
Figure 9.14 Input/Output Data Inversion Function..................................................................... 206
Section 10 Realtime Clock (RTC)
Figure 10.1 Block Diagram of RTC ........................................................................................... 211