Datasheet

Section 12 Timer F
Rev. 2.00 Jul. 04, 2007 Page 240 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
2
1
0
CKSL2
CKSL1
CKSL0
0
0
0
W
W
W
Clock Select L
Select the clock input to TCFL from among four internal
clock sources or external event input.
000: Counting on a rising or falling edge of an external
event (on the TMIF pin)*
001: Counting on a rising or falling edge of an external
event (on the TMIF pin)*
010: Counting on a rising or falling edge of an external
event (on the TMIF pin)*
011: Using prohibited
100: Internal clock: counting on φ/32
101: Internal clock: counting on φ/16
110: Internal clock: counting on φ/4
111: Internal clock: counting on φ
W
/4
Note: * The TMIFEG bit in IEGR selects which edge of an external event is used for counting.
12.3.4 Timer Control/Status Register F (TCSRF)
TCSRF performs counter clear selection, overflow flag setting, and compare match flag setting,
and controls enabling of overflow interrupt requests.
Bit Bit Name
Initial
Value
R/W Description
7 OVFH 0 R/(W)* Timer Overflow Flag H
[Setting condition]
TCFH overflows from H'FF to H'00
[Clearing condition]
Writing of 0 to bit OVFH after reading OVFH = 1
6 CMFH 0 R/(W)* Compare Match Flag H
This is a status flag indicating that TCFH has matched
OCRFH.
[Setting condition]
The TCFH value matches the OCRFH value
[Clearing condition]
Writing of 0 to bit CMFH after reading CMFH = 1