Datasheet

Section 12 Timer F
Rev. 2.00 Jul. 04, 2007 Page 242 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
1 OVIEL 0 R/W Timer Overflow Interrupt Enable L
Selects enabling or disabling of interrupt generation
when TCFL overflows.
0: TCFL overflow interrupt request is disabled
1: TCFL overflow interrupt request is enabled
0 CCLRL 0 R/W Counter Clear L
Selects whether TCFL is cleared when TCFL and
OCRFL match.
0: TCFL clearing by compare match is disabled
1: TCFL clearing by compare match is enabled
Note: * Only 0 can be written to clear the flag.
12.4 Operation
The timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in the output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. The timer F
can also be used as two independent 8-bit timers.
12.4.1 Timer F Operation
The timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in
each of these modes is described below.
(1) Operation in 16-Bit Timer Mode
When the CKSH2 bit is cleared to 0 in TCRF, the timer F operates as a 16-bit timer.
Following a reset, TCF is initialized to H'0000, OCRF to H'FFFF, and TCRF and TCSRF to H'00.
The counter is incremented by an input signal from an external event (TMIF pin). The TMIFEG
bit in IEGR selects which edge of an external event is used for counting.
The timer F counter input clock can be selected from internal clocks or external events according
to settings of bits CKSL2 to CKSL0 in TCRF.