Datasheet

Section 12 Timer F
Rev. 2.00 Jul. 04, 2007 Page 249 of 692
REJ09B0309-0200
(2) TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by
a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data
is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, even if the written data and the counter value match, there is a
probability of a compare match signal being generated and not being generated. As the compare
match signal is output in synchronization with the TCFL clock, a compare match will not result in
compare match signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not
output.
12.6.3 Flag Clearing
When φ
W
/4 is selected as the internal clock, "Interrupt source generation signal" will be operated
with φ
W
and the signal will be outputted with φ
W
width. And, "Overflow signal" and "Compare
match signal" are controlled with 2 cycles of φ
W
signals. Those signals are output with 2-cycle
width of φ
W
(figure 12.7)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of "Interrupt source generation signal", same interrupt request flag is set. (1 in
figure 12.7) And, the timer overflow flag and compare match flag cannot be cleared during the
term of validity of "Overflow signal" and "Compare match signal".
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (2 in figure 12.7) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula.
For ST of (1) formula, please substitute the longest number of execution states in used instruction.
(10 states of RTE instruction when MULXS, DIVXS instruction is not used, 24 states when
MULXS, DIVXS instruction is used)
In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.