Datasheet

Section 13 Timer G
Rev. 2.00 Jul. 04, 2007 Page 255 of 692
REJ09B0309-0200
13.2 Input/Output Pins
Table 13.1 shows the timer G pin configuration.
Table 13.1 Pin Configuration
Pin Name Abbreviation I/O Function
Input capture input TMIG Input Input capture input pin
13.3 Register Descriptions
The timer G has the following registers. For details on the clock halt register 3 (CKSTPR3), see
section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3).
• Timer counter G (TCG)
• Input capture register GF (ICRGF)
• Input capture register GR (ICRGR)
• Timer mode register G (TMG)
• Clock halt register 3 (CKSTPR3)
13.3.1 Timer Counter G (TCG)
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMRF is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details on interrupts, see section 4, Interrupt Controller.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: An input capture signal may be generated when TMIG is modified.