Datasheet

Section 13 Timer G
Rev. 2.00 Jul. 04, 2007 Page 256 of 692
REJ09B0309-0200
13.3.2 Input Capture Register GF (ICRGF)
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details on interrupts, see section 4, Interrupt Controller.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
SUB
(when the noise canceller is not used).
ICRGF is initialized to H'00 upon reset.
13.3.3 Input Capture Register GR (ICRGR)
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details on interrupts, see section 4, Interrupt Controller.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
SUB
(when the noise canceller is not used).
ICRGR is initialized to H'00 upon reset.
13.3.4 Timer Mode Register G (TMG)
TMG is an 8-bit readable/writable register that performs TCG clock selection from four internal
clock sources, counter clear selection, and edge selection for the input capture input signal
interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow
flags.
TMG is initialized to H'00 upon reset.