Datasheet

Section 13 Timer G
Rev. 2.00 Jul. 04, 2007 Page 258 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
4 IIEGS 0 R/W Input Capture Interrupt Edge Select
Selects the input capture input signal edge that
generates an interrupt request.
0: Interrupt generated on rising edge of input capture
input signal
1: Interrupt generated on falling edge of input capture
input signal
3
2
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
Specify whether or not TCG is cleared by the rising
edge, falling edge, or both edges of the input capture
input signal.
00: TCG clearing is disabled
01: TCG cleared by falling edge of input capture input
signal
10: TCG cleared by rising edge of input capture input
signal
11: TCG cleared by both edges of input capture input
signal
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select
Select the clock input to TCG from four internal clock
sources.
00: Internal clock: counting on φ/64
01: Internal clock: counting on φ/32
10: Internal clock: counting on φ/2
11: Internal clock: counting on φ
W
/4
Note: * Only 0 can be written to clear the flag.