Datasheet

Section 13 Timer G
Rev. 2.00 Jul. 04, 2007 Page 260 of 692
REJ09B0309-0200
The noise canceller consists of five latch circuits connected in series and a match detector circuit.
When the noise cancellation function is not used (NCS = 0), the system clock is selected as the
sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the
internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the
rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If
all the outputs do not match, the previous value is retained. After a reset, the noise canceller output
is initialized when the falling edge of the input capture input signal has been sampled five times.
Therefore, after making a setting for use of the noise cancellation function, a pulse with at least
five times the width of the sampling clock is a dependable input capture signal. Even if noise
cancellation is not used, an input capture input signal pulse width of at least 2φ or 2φ
SUB
is
necessary to ensure that input capture operations are performed properly.
Note: * An input capture signal may be generated when the NCS bit is modified.
Figure 13.3 shows an example of noise canceller timing.
In this example, high-level input of not more than five times the width of the sampling clock at the
input capture input pin is eliminated as noise.
Input capture
input signal
Sampling clock
Noise canceler
output
Eliminated as noise
Figure 13.3 Noise Canceller Timing (Example)