Datasheet

Section 13 Timer G
Rev. 2.00 Jul. 04, 2007 Page 261 of 692
REJ09B0309-0200
13.5 Operation
Timer G is an 8-bit timer with built-in input capture and interval functions.
13.5.1 Timer G Functions
Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval
timer function.
The operation of these two functions is described below.
(1) Input Capture Timer Operation
When the TMIG bit in the port mode register F (PMRF) is set to 1, timer G functions as an input
capture timer*.
Upon reset, the timer mode register G (TMG), timer counter G (TCG), input capture register GF
(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.
Following a reset, TCG starts counting on the φ/64 internal clock.
The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG.
When a rising edge/falling edge is detected in the input capture signal input from the TMIG pin,
the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected by IIEGS in
TMG is input, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1 at this time, an
interrupt request is sent to the CPU. For details on interrupts, see section 4, Interrupt Controller.
TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal,
according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the input
capture signal is high, the OVFH bit in TMG is set; if TCG overflows when the input capture
signal is low, the OVFL bit in TMG is set. If the OVIE bit in TMG is 1 when these bits are set,
IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1, timer G sends an interrupt request
to the CPU. For details on interrupts, see section 4, Interrupt Controller.
Timer G has a built-in noise canceller that enables high-frequency component noise to be
eliminated from pulses input from the TMIG pin. For details, see section 13.4, Noise Canceller.
Note: * An input capture signal may be generated when TMIG is modified.