Datasheet

Section 13 Timer G
Rev. 2.00 Jul. 04, 2007 Page 262 of 692
REJ09B0309-0200
(2) Interval Timer Operation
When the TMIG bit in PMRF is cleared to 0, timer G functions as an interval timer.
Following a reset, TCG starts counting on the φ/64 internal clock. The input clock can be selected
from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments on the
selected clock, and when it overflows from H'FF to H'00, the OVFL bit in TMG is set to 1. If the
OVIE bit in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1,
timer G sends an interrupt request to the CPU. For details on interrupts, see section 4, Interrupt
Controller.
13.5.2 Count Timing
TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four
internal clock sources (φ/64, φ/32, φ/2, or φ
W
/4) created by dividing the system clock (φ) or watch
clock (φ
W
).
13.5.3 Input Capture Input Timing
(1) Without Noise Cancellation Function
For input capture input, dedicated input capture functions are provided for rising and falling edges.
Figure 13.4 shows the timing for rising/falling edge input capture input.
Input capture
input signal
Input capture
signal F
Input capture
signal R
φ
Figure 13.4 Input Capture Input Timing (without Noise Cancellation Function)