Datasheet

Section 14 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Jul. 04, 2007 Page 275 of 692
REJ09B0309-0200
14.3.1 Timer Control Register (TCR)
TCR controls TCNT operation for each channel. The TPU has a total of two TCR registers, one
for each channel. TCR should be set when TCNT operation is stopped.
Bit Bit Name
Initial
Value
R/W Description
7  0  Reserved
This bit is always read as 0 and cannot be modified.
6
5
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
These bits select the TCNT counter clearing source.
See table 14.3 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the input clock edge. When the
internal clock is counted using both edges, the input
clock period is halved (e.g. φ/4 both edges = φ/2 rising
edge). Internal clock edge selection is valid when the
input clock is φ/4 or slower. If the input clock is φ/1, this
setting is ignored and count at a rising edge is selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
[Legend] x: Don't care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Timer Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables14.4 and 14.5 for details.