Datasheet

Section 14 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Jul. 04, 2007 Page 277 of 692
REJ09B0309-0200
Table 14.5 TPSC2 to TPSC0 (Channel 2)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2 0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 Internal clock: counts on φ/1024
14.3.2 Timer Mode Register (TMDR)
TMDR sets the operating mode for each channel. The TPU has a total of two TMDR registers, one
for each channel. TMDR should be set when TCNT operation is stopped.
Bit Bit Name
Initial
Value
R/W Description
7, 6  All 1  Reserved
These bits are always read as 1 and cannot be
modified.
5, 4  All 0  Reserved
These bits are always read as 0 and cannot be
modified.
3, 2  All 0  Reserved
The write value should always be 0.
1
0
MD1
MD0
0
0
R/W
R/W
Modes 1 and 0
These bits set the timer operating mode.
See table 14.6 for details.