Datasheet

Section 14 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Jul. 04, 2007 Page 287 of 692
REJ09B0309-0200
14.3.9 Timer Synchro Register (TSYR)
TSYR selects independent operation or synchronous operation of TCNT for each channel.
Synchronous operation is performed for channel in which the corresponding bit in TSYR is set to
1.
Bit Bit Name
Initial
Value
R/W Description
7 to 3  All 0 R/W Reserved
The write value should always be 0.
2
1
SYNC2
SYNC1
0
0
R/W
R/W
Timer Synchro 2 and 1
These bits select whether operation is independent of
or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits must be
set to 1. To set synchronous clearing, in addition to the
SYNC bit, the TCNT clearing source must also be set
by means of bits CCLR1 and CCLR0 in TCR.
0: TCNT_n operates independently (TCNT presetting/
clearing is unrelated to other channels)
1: TCNT_n performs synchronous operation
TCNT synchronous presetting/synchronous clearing
is possible
[Legend] n = 2 or 1
0  0 R/W Reserved
The write value should always be 0.