Datasheet

Section 14 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Jul. 04, 2007 Page 312 of 692
REJ09B0309-0200
14.8.3 Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the last state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
f =
φ
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
14.8.4 Contention between TCNT Write and Clear Operation
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
priority and the TCNT write is not performed.
Figure 14.31 shows the timing in this case.
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N H'0000
Figure 14.31 Contention between TCNT Write and Clear Operation