Datasheet

Section 15 Asynchronous Event Counter (AEC)
Rev. 2.00 Jul. 04, 2007 Page 323 of 692
REJ09B0309-0200
15.3.3 Input Pin Edge Select Register (AEGSR)
AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins.
Bit Bit Name
Initial
Value
R/W Description
7
6
AHEGS1
AHEGS0
0
0
R/W
R/W
AEC Edge Select H
Select rising, falling, or both edge sensing for the AEVH
pin.
00: Falling edge on AEVH pin is sensed
01: Rising edge on AEVH pin is sensed
10: Both edges on AEVH pin are sensed
11: Setting prohibited
5
4
ALEGS1
ALEGS0
0
0
R/W
R/W
AEC Edge Select L
Select rising, falling, or both edge sensing for the AEVL
pin.
00: Falling edge on AEVL pin is sensed
01: Rising edge on AEVL pin is sensed
10: Both edges on AEVL pin are sensed
11: Setting prohibited
3
2
AIEGS1
AIEGS0
0
0
R/W
R/W
IRQAEC Edge Select
Select rising, falling, or both edge sensing for the
IRQAEC pin.
00: Falling edge on IRQAEC pin is sensed
01: Rising edge on IRQAEC pin is sensed
10: Both edges on IRQAEC pin are sensed
11: Setting prohibited
1 ECPWME 0 R/W Event Counter PWM Enable
Controls operation of event counter PWM and selection
of IRQAEC.
0: AEC PWM halted, IRQAEC selected
1: AEC PWM enabled, IRQAEC not selected
0  0 R/W Reserved
This bit can be read from or written to. However, this bit
should not be set to 1.