Datasheet

Section 15 Asynchronous Event Counter (AEC)
Rev. 2.00 Jul. 04, 2007 Page 324 of 692
REJ09B0309-0200
15.3.4 Event Counter Control Register (ECCR)
ECCR controls the counter input clock and IRQAEC/IECPWM.
Bit Bit Name
Initial
Value
R/W Description
7
6
ACKH1
ACKH0
0
0
R/W
R/W
AEC Clock Select H
Select the clock used by ECH.
00: AEVH pin input
01: φ/2
10: φ/4
11: φ/8
5
4
ACKL1
ACKL0
0
0
R/W
R/W
AEC Clock Select L
Select the clock used by ECL.
00: AEVL pin input
01: φ/2
10: φ/4
11: φ/8
3
2
1
PWCK2
PWCK1
PWCK0
0
0
0
R/W
R/W
R/W
Event Counter PWM Clock Select
Select the event counter PWM clock.
000: φ/2
001: φ/4
010: φ/8
011: φ/16
1x0: φ/32
1x1: φ/64
When changing the event counter PWM clock, stop the
PWM by setting the ECPWME bit in AEGSR to 0, and
then change the value of these bits.
0  0 R/W Reserved
This bit can be read from or written to. However, this bit
should not be set to 1.
[Legend]
x: Don't care