Datasheet

Section 15 Asynchronous Event Counter (AEC)
Rev. 2.00 Jul. 04, 2007 Page 325 of 692
REJ09B0309-0200
15.3.5 Event Counter Control/Status Register (ECCSR)
ECCSR controls counter overflow detection, counter resetting, and count-up function.
Bit Bit Name
Initial
Value
R/W Description
7 OVH 0 R/(W)* Counter Overflow H
This is a status flag indicating that ECH has overflowed.
[Setting condition]
ECH overflows from H'FF to H'00
[Clearing condition]
Writing of 0 to bit OVH after reading OVH = 1
6 OVL 0 R/(W)* Counter Overflow L
This is a status flag indicating that ECL has overflowed.
[Setting condition]
ECL overflows from H'FF to H'00 while CH2 is set to 1
[Clearing condition]
Writing of 0 to bit OVL after reading OVL = 1
5  0 R/W Reserved
Although this bit is readable/writable, it should not be
set to 1.
4 CH2 0 R/W Channel Select
Selects how ECH and ECL event counters are used
0: ECH and ECL are used together as a single-channel
16-bit event counter
1: ECH and ECL are used as two-channel 8-bit event
counter
3 CUEH 0 R/W Count-Up Enable H
Enables event clock input to ECH.
0: ECH event clock input is disabled (ECH value is
retained)
1: ECH event clock input is enabled