Datasheet

Rev. 2.00 Jul. 04, 2007 Page xxxv of xl
Tables
Section 1 Overview
Table 1.1
Pin Functions ............................................................................................................ 5
Section 2 CPU
Table 2.1 Operation Notation .................................................................................................21
Table 2.2 Data Transfer Instructions....................................................................................... 22
Table 2.3 Arithmetic Operations Instructions (1) ...................................................................23
Table 2.3 Arithmetic Operations Instructions (2) ...................................................................24
Table 2.4 Logic Operations Instructions................................................................................. 25
Table 2.5 Shift Instructions..................................................................................................... 25
Table 2.6 Bit Manipulation Instructions ................................................................................. 26
Table 2.7 Branch Instructions ................................................................................................. 28
Table 2.8 System Control Instructions.................................................................................... 29
Table 2.9 Block Data Transfer Instructions ............................................................................ 30
Table 2.10 Addressing Modes .................................................................................................. 32
Table 2.11 Absolute Address Access Ranges...........................................................................34
Table 2.12 Effective Address Calculation (1)...........................................................................36
Table 2.12 Effective Address Calculation (2)...........................................................................37
Section 3 Exception Handling
Table 3.1 Exception Sources and Vector Address .................................................................. 48
Table 3.2 Interrupt Sources that Cause a Reset.......................................................................49
Table 3.3 Conditions under which Interrupt Request Flag is Set to 1..................................... 55
Section 4 Interrupt Controller
Table 4.1 Pin Configuration.................................................................................................... 60
Table 4.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities.................................74
Table 4.3 Interrupt Control States...........................................................................................77
Table 4.4 Interrupt Response Times (States) ..........................................................................81
Section 5 Clock Pulse Generator
Table 5.1 Selection of the System Clock Oscillator or On-Chip Oscillator for
the System Clock ....................................................................................................90
Section 6 Power-Down Modes
Table 6.1 Operating Frequency and Wait Time.................................................................... 106
Table 6.2 Transition Mode after SLEEP Instruction Execution and
Interrupt Handling.................................................................................................112
Table 6.3 Internal State in Each Operating Mode................................................................. 115